article

Automating the sizing of transistors in CMOS gates for low-power and high-noise margin operation

Author:

Azam BegAuthors Info & Claims

International Journal of Circuit Theory and Applications, Volume 43, Issue 11

Pages 1637 - 1654

https://doi.org/10.1002/cta.2031

Published: 01 November 2015 Publication History

Abstract

This paper presents an automatic method for sizing the transistors in CMOS gates. The method utilizes a feedback control system to efficiently optimize the transistor sizes in small and large fan-in gates, with the primary goal of enhancing noise robustness as characterized by the static noise margin. The gates retain their robustness under threshold-voltage variations over a range of supply voltages. The optimized gates not only expend reduced power and energy, but also take up less area than the conventional ones. These multi-faceted gains, however, do incur some performance loss. Copyright © 2014 John Wiley & Sons, Ltd.

References

[1]

Moore GE. Cramming more components onto integrated circuits. Electronics 1965; Volume 38 Issue 8: pp.114-117. {Reprinted in Proc. IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998}.

[2]

Intl. Tech. Roadmap for Semiconductors ITRS. SEMATECH. Albany: NY, USA, 2011 {Online}. Available: "http://public.itrs.net/".

[3]

Rabaey JM, Chandrakasan A. Digital Integrated Circuits - A Design Perspective 2^nd ed. Prentice Hall: NJ, USA, 2003.

[4]

Roska T. Circuits, computers, and beyond Boolean logic. Int J Circuit Theory Appl 2007; Volume 35 Issue 5-6: pp.485-496.

[5]

Bansal A, Mukhopadhyay S, Roy K. Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era. IEEE Trans Electr Dev 2007; Volume 54 Issue 6: pp.1409-1419.

[6]

Tawfik SA, Kursun V. Low power and high speed multi threshold voltage interface circuits. IEEE Trans VLSI Syst 2009; Volume 17 Issue 5: pp.638-645.

Digital Library

[7]

Chang J-M, Pedram M. Energy minimization using multiple supply voltages. IEEE Trans VLSI Syst 1997; Volume 5 Issue 4: pp.436-443.

[8]

Calhoun BH, Chandrakasan A. Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm CMOS. Proc. ISSCC, San Francisco, CA, USA, 300-301 and 599, 2005.

[9]

Liu X, Mourad S. Performance of submicron CMOS devices and gates with substrate biasing. Proc. ISCAS, Geneva, Switzerland, 2000, Volume 4, pp.9-12.

[10]

Corsonello P, Lanuzza M, Perri S. Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. Int J Circuit Theory Appl 2014; Volume 42 Issue 1: pp.65-70.

[11]

Albano D, Lanuzza M, Taco R, Crupi F. Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines. Int J Circuit Theory Appl 2014.

[12]

Faraji R, Naji HR, Rahimi-Nezhad M, Arabnejhad M. New SRAM design using body bias technique for low-power and high-speed applications. Int J Circuit Theory Appl 2013.

[13]

Marković D, Wang CC, Alarcón LP, Liu T-T, Rabaey JM. Ultralow-power design in near-threshold region. Proc IEEE 2010; Volume 98 Issue 2: pp.237-252.

[14]

Soeleman H, Roy K. Ultra-low power digital subthreshold logic circuits. Proc. ISLPED, San Diego, CA, USA, 1999; pp.94-96.

Digital Library

[15]

Giustolisi G, Palumbo G, Criscione M, Cutrì F. A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J Solid-State Circ 2003; Volume 38 Issue 1: pp.151-154.

[16]

Hill CF. Noise margin and noise immunity in logic circuits. Microelectr 1968; Volume 1 Issue 4: pp.16-21.

[17]

Flak J, Laiho M. Fault-tolerant programmable logic array for nanoelectronics. Int J Circuit Theory Appl 2012; Volume 40 Issue 12: pp.1233-1247.

[18]

Frustaci F, Lanuzza M, Perri S, Corsonello P. Analyzing noise robustness of wide fan-in dynamic logic gates under process variations. Int J Circuit Theory Appl 2014; Volume 42 Issue 5: pp.452-467.

[19]

Lohstroh J. Static and dynamic noise margins of logic circuits. IEEE J Solid-State Circ 1979; Volume 14 Issue 3: pp.591-598.

[20]

Beg A, Beg A. Reliability of Nano-Scaled Logic Gates Based on Binary Decision Diagrams. 2014 Proc. MSV'14, Las Vegas, NV, USA, pp.1-5, 2014.

[21]

Merino JL, Bota SA, Picos R, Segura J. Alternate characterization technique for static random-access memory static noise margin determination. Int J Circuit Theory Appl 2013; Volume 41: pp.1085-1096.

[22]

Beiu V, Beg A, Ibrahim W, Kharbash F, Alioto M. Enabling sizing for enhancing the static noise margins. Proc. ISQED, Santa Clara, CA, USA, 2013; 278-285.

[23]

Beiu V, Ibrahim W, Beg A, Kharbash F. Towards ultra-low power/voltage using unconventionally sized arrays of transistors. Proc. IEEE-NANO, Birmingham: UK, 2012; pp.1-5.

[24]

Beiu V, Ibrahim W, Beg A, Tache M. On sizing transistors for threshold voltage variations. Proc. DFR. Paris, France, 2012.

[25]

Ibrahim W, Beg A, Beiu V. Highly reliable and low-power full adder cell. Proc. IEEE-NANO, Portland, OR, USA, 2011; pp.500-503.

[26]

Beiu V, Beg A, Ibrahim W. Atto joule gates for the whole voltage range. Proc. IEEE-NANO, Portland, OR, USA, 2011; pp.1424-1429.

[27]

Gupta P, Kahng AB, Sharma P, Sylvester D. Selective gate-length biasing for cost-effective runtime leakage control. Proc. DAC, San Diego, CA, USA, 2004; pp.327-330.

Digital Library

[28]

Venugopal R, Chakravarthi S, Chidambaram PR. Design of CMOS transistors to maximize circuit FOM using a coupled process and mixed-mode simulation methodology. IEEE Electr Dev Lett 2006; Volume 27 Issue 10: pp.863-865.

[29]

Hanson S, Seok M, Sylvester D, Blaauw D. Nanometer device scaling in subthreshold logic and SRAM. IEEE Trans Electr Dev 2008; Volume 55 Issue 1: pp.175-185.

[30]

Bol D, Ambroise R, Flandre D, Legat J-D. Interests and limitations of technology scaling for subthreshold logic. IEEE Trans VLSI Syst 2009; Volume 17 Issue 10: pp.1508-1519.

Digital Library

[31]

Tajalli, Leblebici Y. Design trade-offs in ultra-low-power digital nanoscale CMOS. IEEE Trans Circ & Syst 2011; Volume 58 Issue 9: pp.2189-2200.

[32]

Gupta H, Ghosh B. Transistor size optimization in digital circuits using ant colony optimization for continuous domain. Int J Circuit Theory Appl 2014; Volume 42 Issue 6: pp.642-658.

[33]

Alioto M. Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE Trans Circ & Syst 2010; Volume 57 Issue 7: pp.1597-1607.

[34]

Calhoun BH, Wang A, Verma N, Chandrakasan A. Sub-threshold design: The challenges of minimizing circuit energy. Proc. ISLPED, Tegernsee, Germany, 2006; pp.366-368.

[35]

Blesken M, Lütkemeier S, Rückert U. Multiobjective optimization for transistor sizing of sub-threshold CMOS logic standard cells. Proc. ISCAS, Paris, France, 2010; pp.1480-1483.

[36]

Alioto M, Palumbo G, Poli M. Simple and accurate modeling of the output transition time in nanometer CMOS gates. Int J Circuit Theory Appl 2010; Volume 38 Issue 10: pp.995-1012.

[37]

Beg A, Elchouemi A. Enhancing static noise margin while reducing power consumption. Proc. MWSCAS 2013, Columbus: OH, USA, 2013; pp.348-351.

[38]

Beg A. Automatic Generation of Characterization Circuits - An Application In Academia 2013. Proc. FIE 2013, Oklahoma City, OK, USA, 2013; pp.661-664.

[39]

Beg A. A Web-Based Method For Building And Simulating Standard Cell Circuits - A Classroom Application. Computer Applications in Engineering Education 2014; pp.1-8.

[40]

Beg A. Designing Array-Based CMOS Logic Gates By Using A Feedback Control System. 2014 Proc. SMC 2014, San Diego, CA, USA, 2014 in press.

[41]

SpiceGen Tools {Online}. Available: "http://www.azambeg.com".

[42]

Predictive Technology Model {Online}. Available: "http://ptm.asu.edu"/.

[43]

Zhao W, Cao Y. New generation of predictive technology model for sub-45nm early design exploration. IEEE Trans Electr Dev 2006; Volume 53 Issue 11: pp.2816-2823.

[44]

Berkeley Short-channel IGFET Model, 2011 {Online}. Available: "http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4_LR"

[45]

Ngspice - Mixed mode - Mixed level circuit simulator {Online}. Available: "http://ngspice.sourceforge.net"/.

[46]

Courtland R. The status of Moore's Law: It's complicated. IEEE Spectrum. {Online}. Available: "http://spectrum.ieee.org/semiconductors/devices/the-status-of-moores-law-its-complicated".

[47]

Asenov A, Brown AR, Davies JH, Kaya S, Slavcheva G. Simulation of intrinsic parameter fluctuations in decanometer and nanometer-scale MOSFETs. IEEE Trans Electr Dev 2003; Volume 50 Issue 9: pp.1837-1852.

[48]

Zavyalova L, Lucas K, Zhang Q, Fan Y, Sethi S, Song H, Tyminski J. Analysis of OPC optical model accuracy with detailed scanner information. Proc. SPIE Optical Microlithography, San Jose, CA, USA, 2008; pp.1-12.

[49]

Leigh JR. Applied Control Theory. IEE Press 1988.

[50]

Meijer M, <familyNamePrefix>de</familyNamePrefix>Gyvez J, Otten R. On-chip digital power supply control for system-on-chip applications. Proc. ISLPED, San Diego, CA, USA, 2005; pp.311-314.

Digital Library

[51]

Almeida G, et al. Predictive dynamic frequency scaling for multi-processor systems-on-chip. Proc. ISCAS, Rio De Janeiro, Brazil, 2011; pp.1500-1503.

Cited By

Abbas ZOlivieri M(2018)Optimal transistor sizing for maximum yield in variation-aware standard cell designInternational Journal of Circuit Theory and Applications10.1002/cta.216744:7(1400-1424)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1002/cta.2167
Abbas ZOlivieri MRipp A(2016)Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradationsJournal of Computational Electronics10.1007/s10825-016-0878-215:4(1424-1439)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10825-016-0878-2

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Published In

cover image International Journal of Circuit Theory and Applications

International Journal of Circuit Theory and Applications Volume 43, Issue 11

November 2015

284 pages

ISSN:0098-9886

EISSN:1097-007X

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John Wiley and Sons Ltd.

United Kingdom

Publication History

Published: 01 November 2015

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Cited By

Abbas ZOlivieri M(2018)Optimal transistor sizing for maximum yield in variation-aware standard cell designInternational Journal of Circuit Theory and Applications10.1002/cta.216744:7(1400-1424)Online publication date: 27-Dec-2018
https://dl.acm.org/doi/10.1002/cta.2167
Abbas ZOlivieri MRipp A(2016)Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradationsJournal of Computational Electronics10.1007/s10825-016-0878-215:4(1424-1439)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10825-016-0878-2

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