Computer assisted source-code parallelisation
Pages 22 - 31
Abstract
Many single-processor embedded systems are implemented using a time-triggered co-operative (TTC) scheduler. When considering possible alternatives to such a design, one option is a multi-CPU architecture, created using off-the-shelf processors or SoC techniques. In order to allow the rapid assessment of such design alternatives, we are exploring ways in which single-processor TTC code may be “automatically” converted to a multi-CPU equivalent. In this paper, we discuss the design of a prototype source code conversion tool. The input to this tool is the source code for the tasks of a single processor system using a TTC scheduler. The output from the tool (in the current version) is the equivalent multi-processor code based on either a “domino” scheduler or a shared-clock scheduler. In order to assess the effectiveness of the tool, we have used it it in a non-trivial case study: the results from this study are presented in detail.
References
[1]
Kopetz, H.: Real-Time Systems: Design Principles for Distributed Embedded Applications. Kluwer Academic (1997).
[2]
Siemers, C., Falsett, R., Seyer, R., Ecker, K.: Reliable event-triggered systems for mechatronic applications. Journal of Systems and Software 77 (2005) 17-26.
[3]
Allworth, S.T.: Introduction to Real-Time Software Design. Macmillan (1981).
[4]
Nissanke, N.: Realtime Systems. Prentice-Hall (1997).
[5]
Pont, M.J.: Patterns for Time-Triggered Embedded Systems. Addison-Wesley (2001).
[6]
Storey, N.: Safety-Critical Computer Systems. Addison-Wesley (1996).
[7]
Bate, I.J.: Introduction to scheduling and timing analysis. In: The Use of Ada in Real-Time Systems, IEE Conference Publication 00/034 (2000).
[8]
Ward, N.J.: The static analysis of a safety-critical avionics control system. In: Air Transport Safety: Proceedings of the Safety and Reliability Society Spring Conference, SaRS, Ltd. (1991).
[9]
Baker, T.P., Shaw, A.: The cyclic executive model and ada. Real-Time Systems 1(1) (1989) 7-25.
[10]
Locke, C.D.: Software architecture for hard real-time applications: Cyclic executives vs. fixed priority executives. Real-Time Systems 4(1) (1992) 37-53.
[11]
Pont, M.J.: Embedded C. Addison-Wesley (2002).
[12]
Ayavoo, D., Pont, M.J., Parker, S.: Using simulation to support the design of distributed embedded control systems: A case study. In Koelmans, A., Bystrov, A., Pont, M., eds.: Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne (2004) 54-65.
[13]
Phatrapornnant, T., Pont, M.J.: Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling. IEEE Transactions on Computers 55(2) (2006) 113-124.
[14]
Edwards, T., Pont, M.J., Scotson, P., Crumpler, S.: A test-bed for evaluating and comparing designs for embedded control systems. In Koelmans, A., Bystrov, A., Pont, M., eds.: Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne (2004) 106-126.
[15]
Key, S., Pont, M.J.: Implementing PID control systems using resource-limited embedded processors. In Koelmans, A., Bystrov, A., Pont, M., eds.: Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne (2004) 76-92.
[16]
Bate, I.J.: An Architecture for Distributed Real-Time Systems. University of York, Department of Computer Science, University Technology Centre (UTC). (1997).
[17]
Maaita, A., Pont, M.J.: Using 'planned pre-emption' to reduce levels of task jitter in a time-triggered hybrid scheduler. In: Proceedings of the 2nd UK Embedded Forum. (2005).
[18]
Lysecky, R., Vahid, F.: A study of the speedups and competitiveness of FPGA soft processor cores using dynamic hardware/software partitioning. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, IEEE Computer Society (2005) 18-23.
[19]
Gray, J.: Designing a Simple FPGA-Optimized RISC CPU and System-on-a-Chip. Gray Research LLC, http://www.fpgacpu.org. (2000).
[20]
Buttazzo, G.C.: Rate monotonic vs. EDF: Judgement day. Real-Time Systems 29 (2005) 5-26.
[21]
Rau, B.R., Fisher, J.A.: Instruction-level parallel processing: History, overview, and perspective. The Journal of Supercomputing 7(1-2) (1993) 9-50.
[22]
Johnson, M.: Superscalar Microprocessor Design. Prentice-Hall (1991).
[23]
Torng, H.C., Vassiliadis, S., eds.: Instruction Level Parallel Processors. IEEE Computer Society Press, Los Alamitos, CA (1995).
[24]
Aditya, S., Mahlke, S.A., Rau, B.R.: Code Size Minimization and Retargetable Assembly for Custom EPIC and VLIW Instruction Formats, HPL-2000-141. HP Laboratories, Palo Alto. (2000).
[25]
Aditya, S., Rau, B.R.: Automatic Architecture Synthesis and Compiler Retargeting for VLIW and EPIC Processors, HPL-1999-93. HP Laboratories, Palo Alto. (1999).
[26]
Pillai, S., Jacome, M.F.: Compiler-directed ILP extraction for clustered VLIW/EPIC machines: Predication, speculation and modulo scheduling. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, IEEE Computer Society (2003) 422-427.
[27]
Rajagopalan, S., Rajan, S.P., Malik, S., Rigo, S., Araujo, G., Takayama, K.: A retargetable VLIW compiler framework for DSPs with instruction-level parallelism. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 (2001) 1319.
[28]
Halambi, A., Grun, P., Ganesh, V., Khare, A., Dutt, N., Nicolau, A.: EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In: Proceedings of the European Conference on Design, Automation and Test (DATE), Munich, Germany, IEEE Computer Society (1999) 485.
[29]
Henzinger, T.A., Benjamin, H., Kirsch, C.M.: Embedded control systems development with giotto. SIGPLAN Notices 36 (2001) 64.
[30]
Jie, L., Lee, E.A.: Timed multitasking for real-time embedded software. IEEE Control Systems Magazine 23 (2003) 65.
[31]
Mellor, S.J.: Automatic code generation from UML models. C++ Report 11(4) (1999) 28-33 automatic code generation;UML;high-level language compilers;notation;object-oriented systems;.
[32]
Mwelwa, C., Pont, M.J., Ward, D.: Code generation supported by a pattern-based design methodology. In Koelmans, A., Bystrov, A., Pont, M., eds.: Proceedings of the 1st UK Embedded Forum, University of Newcastle upon Tyne (2004) 36-55.
[33]
Vidler, P.J., Pont, M.J.: Automatic conversion from 'single processor' to 'multiprocessor' software architectures for embedded control systems. In Koelmans, A., Bystrov, A., Pont, M.J., Ong, R., Brown, A., eds.: Proceedings of the 2nd UK Embedded Forum. (2005).
[34]
Ayavoo, D., Pont, M.J., Parker, S.: A 'hardware-in-the-loop' testbed representing the operation of a cruise-control system in a passenger car. In: Proceedings of the 2nd UK Embedded Forum. (2005).
[35]
ISO/DIS 11898: Road Vehicles -- Interchange of Digital Information -- Controller Area Network (CAN) for High Speed Communication. (1992).
[36]
Nahas, M., Short, M.J., Pont, M.J.: The impact of bit stuffing on the real-time performance of a distributed control system. In: Proceedings of the 10th International CAN Conference, Rome (2005).
[37]
Marti, P., Fuertes, J.M., Fohler, G.: A control performance metric for real-time timing constraints. In: Proceedings of the 14th Euromicro International Conference on Real-Time Systems. (2002).
[38]
Dorf, R.C., Bishop, R.H.: Modern Control Systems. Seventh edn. Addison-Wesley (1995).
Recommendations
Detect Related Bugs from Source Code Using Bug Information
COMPSAC '10: Proceedings of the 2010 IEEE 34th Annual Computer Software and Applications ConferenceOpen source projects often maintain open bug repositories during development and maintenance, and the reporters often point out straightly or implicitly the reasons why bugs occur when they submit them. The comments about a bug are very valuable for ...
CODES: mining source code descriptions from developers discussions
ICPC 2014: Proceedings of the 22nd International Conference on Program ComprehensionProgram comprehension is a crucial activity, preliminary to any software maintenance task. Such an activity can be difficult when the source code is not adequately documented, or the documentation is outdated. Differently from the many existing ...
Do bugs lead to unnaturalness of source code?
ESEC/FSE 2022: Proceedings of the 30th ACM Joint European Software Engineering Conference and Symposium on the Foundations of Software EngineeringTexts in natural languages are highly repetitive and predictable because of the naturalness of natural languages. Recent research validated that source code in programming languages is also repetitive and predictable, and naturalness is an inherent ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
May 2006
1044 pages
ISBN:3540340793
Sponsors
- The University of Perugia: The University of Perugia
- Institute of Electrical Engineers (IEE), UK: Institute of Electrical Engineers (IEE), UK
- The University of Minnesota, Minneapolis, MN: The University of Minnesota, Minneapolis, MN
- UOC: University of Calgary
- The Queen's University of Belfast: The Queen's University of Belfast
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 08 May 2006
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 18 Dec 2024