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EXPRESSION: a language for architecture exploration through compiler/simulator retargetability

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Alex NicolauAuthors Info & Claims

DATE '99: Proceedings of the conference on Design, automation and test in Europe

Pages 100 - es

https://doi.org/10.1145/307418.307549

Published: 01 January 1999 Publication History

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References

[1]

{1} G. Goosens et al. CHESS: Retargetable code generation for embedded DSP processors. In Code Generation for Embedded Processors. Kluwer, 1997.

Google Scholar

[2]

{2} G. Hadjiyiannis et al. ISDL: An instruction set description language for retargetability. In Proc. DAC, 1997.

Digital Library

Google Scholar

[3]

{3} H. Yasuura et al. A programming language for processor based embedded systems. In Proc. APCHDL, 1998.

Google Scholar

[4]

{4} J. Gyllenhaal et al. Optimization of machine descriptions for efficient use. In Proc. 29th Annual International Symposium on Microarchitecture, 1996.

Digital Library

Google Scholar

[5]

{5} P. Paulin et al. FlexWare: A flexible firmware development environment for embedded systems. In Proc. Dagstuhl Code Generation Workshop, 1994.

Google Scholar

[6]

{6} R. Leupers et al. Retargetable generation of code selectors from HDL processor models. In Proc. EDTC, 1997.

Digital Library

Google Scholar

[7]

{7} V. Zivojnovic et al. LISA - machine description language and generic machine model for HW/SW co-design. In IEEE Workshop on VLSI Signal Processing, 1996.

Google Scholar

[8]

{8} M. Freericks. The nML machine description formalism. Technical Report TR SMIMP/DIST/08, TU Berlin CS Dept., 1993.

Google Scholar

[9]

{9} P. Grun, F. Balasa, and N. Dutt. Memory size estimation for multimedia applications. In Proc. CODES/CACHE, 1998.

Digital Library

Google Scholar

[10]

{10} P. Grun, A. Halambi, A. Khare, V. Ganesh, N. Dutt, and A. Nicolau. EXPRESSION: An ADL for system level design exploration. Technical Report TR 98-29, University Of California, Irvine, 1998.

Google Scholar

[11]

{11} J. Gyllenhaal. A machine description language for compilation. Master's thesis, Dept. of EE, UIUC, IL., 1994.

Google Scholar

[12]

{12} S. Hanono and S. Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Proc. DAC, 1998.

Digital Library

Google Scholar

[13]

{13} R. Leupers and P. Marwedel. Retargetable code generation based on structural processor descriptions. Design Automation for Embedded Systems, 3(1), 1998.

Google Scholar

[14]

{14} MOTOROLA Inc. DSP56000 24-Bit Digital Signal Processor Family Manual, 1995.

Google Scholar

[15]

{15} P. Panda, N. Dutt, and A. Nicolau. Architectural exploration and optimization of local memory in embedded systems. In Proc. ISSS, 1997.

Digital Library

Google Scholar

[16]

{16} C. Siska. A processor description language supporting retargetable multipipeline dsp program development tools. In Proc. ISSS, December 1998.

Digital Library

Google Scholar

[17]

{17} TEXAS INSTRUMENTS. TMS320C62x/C67x CPU and Instruction Set Reference Guide, 1998.

Google Scholar

[18]

{18} Trimaran Release: http://www.trimaran.org. The MDES User Manual, 1998.

Google Scholar

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Xiao XLiu Z(2024)An Adaptive Instruction Set Encoding Automatic Generation Method for VLIWAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0834-5_17(283-300)Online publication date: 12-Mar-2024
https://doi.org/10.1007/978-981-97-0834-5_17
Xiao XLiu Z(2023)ISADL: An Instruction Set Architecture Description Language for VLIW2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS60453.2023.00022(92-99)Online publication date: 17-Dec-2023
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Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
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Index Terms

EXPRESSION: a language for architecture exploration through compiler/simulator retargetability
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
    2. General programming languages
      1. Language types

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DATE '99: Proceedings of the conference on Design, automation and test in Europe

January 1999

730 pages

ISBN:1581131216

DOI:10.1145/307418

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1999

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DATE99: Design Automation and Test in Europe Conference and Exhibition 1999

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Cited By

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Xiao XLiu Z(2024)An Adaptive Instruction Set Encoding Automatic Generation Method for VLIWAlgorithms and Architectures for Parallel Processing10.1007/978-981-97-0834-5_17(283-300)Online publication date: 12-Mar-2024
https://doi.org/10.1007/978-981-97-0834-5_17
Xiao XLiu Z(2023)ISADL: An Instruction Set Architecture Description Language for VLIW2023 IEEE 29th International Conference on Parallel and Distributed Systems (ICPADS)10.1109/ICPADS60453.2023.00022(92-99)Online publication date: 17-Dec-2023
https://doi.org/10.1109/ICPADS60453.2023.00022
Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
Jiang SOu YPan PBatten C(2021)UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling2021 58th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18074.2021.9586130(883-888)Online publication date: 5-Dec-2021
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Weng JLiu SDadu VWang ZShah PNowatzki T(2020)DSAGEN: Synthesizing Programmable Spatial Accelerators2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)10.1109/ISCA45697.2020.00032(268-281)Online publication date: May-2020
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Carpenter PRamirez AAyguade E(2019)The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors10.1007/978-3-662-58834-5_5(79-99)Online publication date: 23-Feb-2019
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Shrivastava ACai J(2017)Hardware-Aware CompilationHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_26-1(1-33)Online publication date: 8-Apr-2017
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Okuda KTakeyama HFanucci LTeich J(2016)Decision tree generation for decoding irregular instructionsProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972179(1592-1597)Online publication date: 14-Mar-2016
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