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Design verification of large scientific computers

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Howard E. KrohnAuthors Info & Claims

DAC '77: Proceedings of the 14th Design Automation Conference

Pages 354 - 361

Published: 01 January 1977 Publication History

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Abstract

Large scientific computers containing 2 million gates can be simulated using a combination of block simulation and gate simulation of 450, 00O gates.

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McWilliams T(1988)Verification of timing constraints on large digital systemsPapers on Twenty-five years of electronic design automation10.1145/62882.62928(388-396)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62928
Goates GHefferan PSmith RHarris ROfek HO'Neill L(1985)Star's envoling design environmentProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317949(584-590)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317949
Abramovici MLevendel YMenon PCrabbe JRadke COfek H(1982)A logic simulation machineProceedings of the 19th Design Automation Conference10.5555/800263.809188(65-73)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809188
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Index Terms

Design verification of large scientific computers
1. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits

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Logic verification system for very large computers using LSI's
DAC '79: Proceedings of the 16th Design Automation Conference

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Design of large ALUs using multiple PLA macros

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DAC '77: Proceedings of the 14th Design Automation Conference

January 1977

507 pages

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IEEE Press

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Published: 01 January 1977

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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McWilliams T(1988)Verification of timing constraints on large digital systemsPapers on Twenty-five years of electronic design automation10.1145/62882.62928(388-396)Online publication date: 1-Jun-1988
https://dl.acm.org/doi/10.1145/62882.62928
Goates GHefferan PSmith RHarris ROfek HO'Neill L(1985)Star's envoling design environmentProceedings of the 22nd ACM/IEEE Design Automation Conference10.5555/317825.317949(584-590)Online publication date: 1-Jun-1985
https://dl.acm.org/doi/10.5555/317825.317949
Abramovici MLevendel YMenon PCrabbe JRadke COfek H(1982)A logic simulation machineProceedings of the 19th Design Automation Conference10.5555/800263.809188(65-73)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809188
Abramovici MLevendel YMenon PSzygenda SHughes JBlanton MWagner TFrailey DGunter TMcLeavy CLipovski JMalek M(1982)A logic simulation machineProceedings of the 9th annual symposium on Computer Architecture10.5555/800048.801723(148-157)Online publication date: 26-Apr-1982
https://dl.acm.org/doi/10.5555/800048.801723
Abramovici MLevendel YMenon P(1982)A logic simulation machineACM SIGARCH Computer Architecture News10.1145/1067649.80172310:3(148-157)Online publication date: 1-Apr-1982
https://dl.acm.org/doi/10.1145/1067649.801723
Krohn H(1981)Vector coding techniques for high speed digital simulationProceedings of the 18th Design Automation Conference10.5555/800073.802354(525-529)Online publication date: 29-Jun-1981
https://dl.acm.org/doi/10.5555/800073.802354
McWilliams THassler ESmith RPistilli PAbel LCrabbe JBening LShaklee DRadke C(1980)Verification of timing constraints on large digital systemsProceedings of the 17th Design Automation Conference10.1145/800139.804523(139-147)Online publication date: 23-Jun-1980
https://dl.acm.org/doi/10.1145/800139.804523
Bening LMagnuson WCairns JThomas DLoomis HFrew RKeiner BBurke DStaller JWilcox PGoldfein AGray JLerman HMcDonald POfek HEisenberg HNash DSrch RSmith RParke FGibson D(1979)Developments in computer simulation of gate level physical logicProceedings of the 16th Design Automation Conference10.5555/800292.811774(561-567)Online publication date: 25-Jun-1979
https://dl.acm.org/doi/10.5555/800292.811774
Chen RCoffman JSzygenda SHightower DSmith RHumcke DRadke @Hassler EPistilli PShaklee D(1978)Multi-sim, a dynamic multi-level simulatorProceedings of the 15th Design Automation Conference10.5555/800095.803119(386-391)Online publication date: 19-Jun-1978
https://dl.acm.org/doi/10.5555/800095.803119
Wold MSzygenda SHightower DSmith RHumcke DRadke @Hassler EPistilli PShaklee D(1978)Design verification and performance analysisProceedings of the 15th Design Automation Conference10.5555/800095.803101(264-270)Online publication date: 19-Jun-1978
https://dl.acm.org/doi/10.5555/800095.803101
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Recommendations

Logic verification system for very large computers using LSI's

Design of large ALUs using multiple PLA macros

R70-5 The Effect of IC's on the Design of Analog Computers

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