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Prediction of wiring space requirements for LSI

Authors:

W. R. Heller,

W. F. Michail,

W. E. DonathAuthors Info & Claims

DAC '77: Proceedings of the 14th Design Automation Conference

Pages 32 - 42

Published: 01 January 1977 Publication History

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Abstract

A stochastic model is developed for estimating wiring space requirements for one-dimensional layouts. This model uses as input the number of devices in the complex to be wired, the average length of a connection, and the average number of connections per device, to compute the probability of successfully wiring the devices as a function of the number of tracks provided.

A heuristic approach is used to extend this model to the two-dimensional case, and tested against experimen-tal studies. Satisfactory agreement is found between a priori calculations of track requirements for the two-dimensional case against global wiring solutions for artificially generated problems, and for some layouts of actual logic complexes.

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W.E. Donath, "Statistical Properties of the Placement of a Graph", SIAM J. Appl. Math. 16 (1968) pp. 376-387.

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W.E. Donath, "Placement and Average Interconnection Lengths of Computer Logic", IBM Research Report 4610, to be published IEEE Journal of Solid State.

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B.S. Landman and R. L. Russo, "On a Pin Versus Block Relationship for Partitions of Logic Graphs", IEEE Trans. on Computers C-20 (1971) pp. 1469-1479.

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W.E. Donath, "Equivalence of Memory to Random Logic", IBM Journal of Research and Development 18 (1974) pp. 401-407; see also "Stochastic Model of the Computer Logic Design Process", IBM Research Report RC 3136.

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Cited By

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Farrahi AHathaway DWang MSarrafzadeh M(2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855839
Li PNag PMaly WStroobandt DChristie PKahng A(2000)Cost based tradeoff analysis of standard cell designsProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333043(129-135)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333043
Kusnadi Carothers JWong D(1999)A method of measuring nets routability for MCM's general area routing problemsProceedings of the 1999 international symposium on Physical design10.1145/299996.300069(186-192)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300069
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Index Terms

Prediction of wiring space requirements for LSI
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Integrated circuits

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DAC '77: Proceedings of the 14th Design Automation Conference

January 1977

507 pages

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IEEE Press

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Published: 01 January 1977

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Farrahi AHathaway DWang MSarrafzadeh M(2000)Quality of EDA CAD ToolsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855839Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855839
Li PNag PMaly WStroobandt DChristie PKahng A(2000)Cost based tradeoff analysis of standard cell designsProceedings of the 2000 international workshop on System-level interconnect prediction10.1145/333032.333043(129-135)Online publication date: 8-Apr-2000
https://dl.acm.org/doi/10.1145/333032.333043
Kusnadi Carothers JWong D(1999)A method of measuring nets routability for MCM's general area routing problemsProceedings of the 1999 international symposium on Physical design10.1145/299996.300069(186-192)Online publication date: 12-Apr-1999
https://dl.acm.org/doi/10.1145/299996.300069
Minai AWilliams RBlake F(1987)A discrete heuristics approach to predictive evaluation of semi-custom IC layoutsProceedings of the 24th ACM/IEEE Design Automation Conference10.1145/37888.38010(770-776)Online publication date: 1-Oct-1987
https://dl.acm.org/doi/10.1145/37888.38010
Kurdahi FParker AThomas D(1986)PLESTProceedings of the 23rd ACM/IEEE Design Automation Conference10.5555/318013.318088(467-473)Online publication date: 2-Jul-1986
https://dl.acm.org/doi/10.5555/318013.318088
Sastry SParker ALambert POfek HO'Neill LPistilli PLosleben PNash JShaklee DPreas BLerman H(1984)On the relation between wire length distributions and placement of logic on master slice ICsProceedings of the 21st Design Automation Conference10.5555/800033.800891(710-711)Online publication date: 25-Jun-1984
https://dl.acm.org/doi/10.5555/800033.800891
Jennings PRadke COfek HShaklee DLosleben PNash JPistilli PLambert PPreas BLerman H(1983)A topology for semicustom array-structured LSI devices, and their automatic customisationProceedings of the 20th Design Automation Conference10.5555/800032.800743(675-681)Online publication date: 27-Jun-1983
https://dl.acm.org/doi/10.5555/800032.800743
Donze RSanders JJenkins MSporzynski GCrabbe JRadke COfek H(1982)Philo-a VLSI design systemProceedings of the 19th Design Automation Conference10.5555/800263.809202(163-169)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809202
Collins CCrabbe JRadke COfek H(1982)IBM 3081 system overview and technologyProceedings of the 19th Design Automation Conference10.5555/800263.809190(75-82)Online publication date: 1-Jan-1982
https://dl.acm.org/doi/10.5555/800263.809190

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Optimizing wiring space in slicing floorplans

Influence on LSI package wireability of via availability and wiring track accessibility

Minimum-Area Wiring for Slicing Structures

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