A discrete heuristics approach to predictive evaluation of semi-custom IC layouts
Pages 770 - 776
Abstract
The significant computational requirements of VLSI layout suggest that it may be desirable to estimate the feasibility of a task before actually performing the task. The system described in this paper uses a discrete heuristics approach to estimate the future quality of a semi-custom layout before any placement or routing is done. It does this evaluation with respect to critical parameters such as routability, area utilization, and wire length, using heuristics arranged in a discrete graph structure. The system can handle user-specified non-rectangular layout shapes. Its rule-based structure allows easy observation and modification of individual heuristics for the purposes of “fine tuning.” The system also detects potential problems and suggests possible solutions.
References
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T.C. Hu and Ernest S. Kuh, "Theory and Concepts of Circuit Layout," pp. 3-18, in VLSI Circuit Layout: Theory and Design, ed. Ernest S. Kuh, IEEE Press, 1985.
[2]
ltrt Soukup, "Circuit Layout," Proceedings of IEEE, vol. 69, pp. 1281-1304, October 1981.
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W.E. Donath, "Placement and Average Interconnection Length of Computer Logic," IEEE Transactions on Circuits and Systems., vol. CAS-26, pp. 272-277, Aprtl 1979.
[4]
W.R. Heller, W.F. Mtkhail, and W.E. Donath, "Prediction of Wiring Space Requirements for LSI," Proceedings of the 14th Design Automation Conference, pp. 32-42, 1977.
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M. Feuer, "Connectivity of Random Logic," 1EEETransactions on Computers, vol. C-31, pp. 29-33, January 1982.
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A.A. E1 Gamal, "Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits," IEEE Transactions on Circuits and Systems, vol. CAS-28, pp. 127-138, February 1981.
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A.A. E1 Gamal and Z.A. Syed, "A Stochastic Model for Interconnections in Custom Integrated Circuits," IEEE Transactions on Circuits and Systems, vol. CAS-28, pp. 888-894, September 1981.
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W.R. Heller, C.G. Hsl, and W,F. Mikhail, "Wlrabillty--Destgntng Wiring Space for Chips and Chip Packages," 1EEE Design & Test, pp. 43-51, August 1984.
[9]
S. Sastry and A.C. Parker, "Stochastic Models for Wirabtlity Analysis of Gate Arrays," IEEE Transactions on Computer-Aided Design, vol. CAD-5, pp. 52-65, january 1986.
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F.J. Kurdahl and A.C. Parker, "PLEST: A Program for Area Estimation of VLSI Integrated Circuits," Proceedings of the 23rd Design Automation Conference, pp. 467-473, 1986.
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N. Soong and A. Patel, "Wirability Expert System," Computer-aided Design, vol. 18, no. 9, pp. 497-501, Nov 1986.
Index Terms
- A discrete heuristics approach to predictive evaluation of semi-custom IC layouts
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Published: 01 October 1987
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