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Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor

Authors: Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. AbrahamAuthors Info & Claims

Proceedings of the IEEE International Test Conference on Test and Design Validity

Pages 160 - 166

Published: 20 October 1996 Publication History

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Krishnaswamy VCasas JTetzlaff TDe Micheli G(2000)A switch level fault simulation environmentProceedings of the 37th Annual Design Automation Conference10.1145/337292.337777(780-785)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337777
Lentz KHeller JMontessoro P(1999)System Verification Using Multilevel Concurrent SimulationIEEE Micro10.1109/40.74879719:1(60-67)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1109/40.748797

Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
2. Computer systems organization

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Proceedings of the IEEE International Test Conference on Test and Design Validity

October 1996

913 pages

ISBN:0780335414

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IEEE Computer Society

United States

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Published: 20 October 1996

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Krishnaswamy VCasas JTetzlaff TDe Micheli G(2000)A switch level fault simulation environmentProceedings of the 37th Annual Design Automation Conference10.1145/337292.337777(780-785)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337777
Lentz KHeller JMontessoro P(1999)System Verification Using Multilevel Concurrent SimulationIEEE Micro10.1109/40.74879719:1(60-67)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1109/40.748797

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Recommendations

Distributed mixed level logic and fault simulation

Distributed logic simulation: time-first evaluation vs. event driven algorithms

Delay Fault Testability on Two-Rail Logic Circuits

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