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A switch level fault simulation environment

Authors:

V. Krishnaswamy,

J. Casas,

T. TetzlaffAuthors Info & Claims

DAC '00: Proceedings of the 37th Annual Design Automation Conference

Pages 780 - 785

https://doi.org/10.1145/337292.337777

Published: 01 June 2000 Publication History

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Abstract

This paper presents a fault simulation environment which accepts pure switch level or mixed switch/RT level descriptions of the design under test. Switch level fault injection strategies for the stuck-at, transition and logic bridge models are presented. A fault simulation algorithm is presented, along with design issues and optimizations. The fault simulation algorithm places no restrictions on the circuit styles used to implement designs. Mixed level simulation issues are discussed. Fault simulation performance numbers on large industrial benchmarks are reported.

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Cited By

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Na J(2013)A Novel Simulation Fault Injection using Electronic Systems Level Simulation ModelsIEEE Design & Test10.1109/MDT.2009.128(1-1)Online publication date: 2013
https://doi.org/10.1109/MDT.2009.128
Lee DNa J(2009)A Novel Simulation Fault Injection Method for Dependability AnalysisIEEE Design & Test of Computers10.1109/MDT.2009.13526:6(50-61)Online publication date: Nov-2009
https://doi.org/10.1109/MDT.2009.135
Javaheri RSedaghat R(2009)Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologiesMicroelectronics Reliability10.1016/j.microrel.2008.11.01049:2(178-185)Online publication date: Mar-2009
https://doi.org/10.1016/j.microrel.2008.11.010
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A switch level fault simulation environment

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Published In

DAC '00: Proceedings of the 37th Annual Design Automation Conference

June 2000

819 pages

ISBN:1581131879

DOI:10.1145/337292

Chairman:
Giovanni De Micheli
Stanford Univ., Stanford, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 2000

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DAC00: ACM/IEEE-CAS/EDAC Design Automation Conference

June 5 - 9, 2000

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Na J(2013)A Novel Simulation Fault Injection using Electronic Systems Level Simulation ModelsIEEE Design & Test10.1109/MDT.2009.128(1-1)Online publication date: 2013
https://doi.org/10.1109/MDT.2009.128
Lee DNa J(2009)A Novel Simulation Fault Injection Method for Dependability AnalysisIEEE Design & Test of Computers10.1109/MDT.2009.13526:6(50-61)Online publication date: Nov-2009
https://doi.org/10.1109/MDT.2009.135
Javaheri RSedaghat R(2009)Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologiesMicroelectronics Reliability10.1016/j.microrel.2008.11.01049:2(178-185)Online publication date: Mar-2009
https://doi.org/10.1016/j.microrel.2008.11.010
Ladhar AMohamed Masmoudi Laroussi Bouzaida (2008)Extraction and simulation of potential bridging faults and open defects affecting standard cell libraries2008 2nd International Conference on Signals, Circuits and Systems10.1109/ICSCS.2008.4746914(1-6)Online publication date: Nov-2008
https://doi.org/10.1109/ICSCS.2008.4746914
Sanada M(2008)Voltage-based fault path tracing by transistor operating point analysisMicroelectronics Reliability10.1016/j.microrel.2008.07.05548:8-9(1533-1538)Online publication date: Aug-2008
https://doi.org/10.1016/j.microrel.2008.07.055
Dongok Kim Amyeen MSrikanth Venkataraman Pomeranz ISwagato Basumallick Landau B(2007)Testing for systematic defects based on DFM guidelines2007 IEEE International Test Conference10.1109/TEST.2007.4437603(1-10)Online publication date: Oct-2007
https://doi.org/10.1109/TEST.2007.4437603
Amyeen MNayak DVenkataraman S(2006)Improving Precision Using Mixed-level Fault Diagnosis2006 IEEE International Test Conference10.1109/TEST.2006.297661(1-10)Online publication date: Oct-2006
https://doi.org/10.1109/TEST.2006.297661
Javaheri MSedaghat RKant LZalev J(2006)Verification and fault synthesis algorithm at switch-levelMicroprocessors and Microsystems10.1016/j.micpro.2005.12.00230:4(199-208)Online publication date: Jun-2006
https://doi.org/10.1016/j.micpro.2005.12.002
Ejlali AMiremadi EGetreu IFix LLavagno L(2003)Switch-level emulationProceedings of the 40th annual Design Automation Conference10.1145/775832.775996(644-649)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775996
DB SAl-Khalili DRozon C(2003)IC bridge fault modeling for IP blocks using neural network-based VHDL saboteursIEEE Transactions on Computers10.1109/TC.2003.123452652:10(1285-1297)Online publication date: 1-Oct-2003
https://dl.acm.org/doi/10.1109/TC.2003.1234526
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