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Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs

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Kyoji ChibaAuthors Info & Claims

DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation Conference

Pages 404 - 410

Published: 02 July 1986 Publication History

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Abstract

Placement algorithms optimizing signal delay as well as wirability for high-speed ECL masterslice LSI's are proposed. Equivalent constraints of wire length for clock skew, data path delay, and wired-OR are classified according to upper and lower limits. To maintain such limits, a top-down method utilizing an augmented two-dimensional clustering placement with “scope” and “zone”, which are new concepts representing limits, and an iterative weighted improvement method are presented. Such algorithms are applied to hundreds of 2 K and 5 K gate ECL masterslice LST's for a newly developed high-end mainframe computer, the Hitachi M-680H. Through such algorithms, the physical design is greatly improved by guaranteeing high wirability and improving electrical characteristics.

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Cited By

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Terai HGemma KNagao YSatoh YOhno YLorenzetti M(1994)Basic concept of cooperative timing-driven design automation technology for high speed RISC processorProceedings of the 31st annual Design Automation Conference10.1145/196244.196371(262-269)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196371
Hamada TCheng CChau PDunlop A(1993)PrimeProceedings of the 30th international Design Automation Conference10.1145/157485.165015(531-536)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.165015
Gao TVaidya PLiu CSchweikert D(1992)A performance driven macro-cell placement algorithmProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.119627(147-152)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.119627
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Index Terms

Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs
1. Applied computing
  1. Physical sciences and engineering
    1. Engineering
2. Hardware

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Published In

DAC '86: Proceedings of the 23rd ACM/IEEE Design Automation Conference

July 1986

835 pages

ISBN:0818607025

Chairman:
Don Thomas
IBM, Thomas J. Watson Research Center, Yorktown Heights, NY

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IEEE Press

Publication History

Published: 02 July 1986

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DAC '86 Paper Acceptance Rate 124 of 300 submissions, 41%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Terai HGemma KNagao YSatoh YOhno YLorenzetti M(1994)Basic concept of cooperative timing-driven design automation technology for high speed RISC processorProceedings of the 31st annual Design Automation Conference10.1145/196244.196371(262-269)Online publication date: 6-Jun-1994
https://dl.acm.org/doi/10.1145/196244.196371
Hamada TCheng CChau PDunlop A(1993)PrimeProceedings of the 30th international Design Automation Conference10.1145/157485.165015(531-536)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.165015
Gao TVaidya PLiu CSchweikert D(1992)A performance driven macro-cell placement algorithmProceedings of the 29th ACM/IEEE Design Automation Conference10.5555/113938.119627(147-152)Online publication date: 1-Jul-1992
https://dl.acm.org/doi/10.5555/113938.119627
Ogawa YItoh TMiki YIshii TSato YToyoshima RNewton A(1991)Timing- and constraint-oriented placement for interconnected LSIs in mainframe designProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127676(253-258)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127676
Terai HGoto FWakai KKozawa TEdagawa MHososaka SHashimoto MNewton A(1991)Basic concepts of timing-oriented design automation for high-performance mainframe computersProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127663(193-198)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127663
Sutanthavibul SShragowitz ENewton A(1991)Dynamic prediction of critical paths and nets for constructive timing-driven placementProceedings of the 28th ACM/IEEE Design Automation Conference10.1145/127601.127165(632-635)Online publication date: 1-Jun-1991
https://dl.acm.org/doi/10.1145/127601.127165
Terai MTakahashi KSato KSmith R(1991)A new min-cut placement algorithm for timing assurance layout design meeting net length constraintProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123234(96-102)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123234
Sutanthavibul SShragowitz ESmith R(1991)An adaptive timing-driven layout for high speed VLSIProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123233(90-95)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123233
Fujihara YSekiyama YIshibashi YYanaka MThomas D(1989)DYNAJUST: an efficient automatic routing technique optimizing delay conditionsProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74531(791-794)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74531
Jackson MKuh EThomas D(1989)Performance-driven placement of cell based IC'sProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74444(370-375)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74444
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