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Basic concept of cooperative timing-driven design automation technology for high speed RISC processor: HARP-1

Authors:

Yasuhiro OhnoAuthors Info & Claims

DAC '94: Proceedings of the 31st annual Design Automation Conference

Pages 262 - 269

https://doi.org/10.1145/196244.196371

Published: 06 June 1994 Publication History

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References

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Cited By

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Sato YIkeya TNakao MNagumo T(2000)A BIST Approach for Very Deep Sub-Micron (VDSM) DefectsProceedings of the 2000 IEEE International Test Conference10.5555/839295.843635Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843635
Kikuchi JSasaki THashimoto TMiyamoto KYoshida K(2000)Delay-optimal wiring plan for the microprocessor of high performance computing machinesProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368629(265-270)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368629
Sato YIkeya TNakao MNagumo T(2000)A BIST approach for very deep sub-micron (VDSM) defectsProceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)10.1109/TEST.2000.894216(283-291)Online publication date: 2000
https://doi.org/10.1109/TEST.2000.894216
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Index Terms

Basic concept of cooperative timing-driven design automation technology for high speed RISC processor: HARP-1
1. Computer systems organization
  1. Architectures
    1. Serial architectures
2. Hardware
  1. Hardware validation
    1. Functional verification
  2. Integrated circuits

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Published In

DAC '94: Proceedings of the 31st annual Design Automation Conference

June 1994

739 pages

ISBN:0897916530

DOI:10.1145/196244

Chairman:
Michael Lorenzetti
Mentor Graphics Corp., Wilsonville, OR

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 June 1994

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DAC94

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EDAC
SIGDA
IEEE-CAS

DAC94: The 31st ACM/IEEE-CAS/EDAC Design Automation Conference

June 6 - 10, 1994

California, San Diego, USA

Acceptance Rates

DAC '94 Paper Acceptance Rate 100 of 260 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

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Sato YIkeya TNakao MNagumo T(2000)A BIST Approach for Very Deep Sub-Micron (VDSM) DefectsProceedings of the 2000 IEEE International Test Conference10.5555/839295.843635Online publication date: 3-Oct-2000
https://dl.acm.org/doi/10.5555/839295.843635
Kikuchi JSasaki THashimoto TMiyamoto KYoshida K(2000)Delay-optimal wiring plan for the microprocessor of high performance computing machinesProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368629(265-270)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368629
Sato YIkeya TNakao MNagumo T(2000)A BIST approach for very deep sub-micron (VDSM) defectsProceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)10.1109/TEST.2000.894216(283-291)Online publication date: 2000
https://doi.org/10.1109/TEST.2000.894216
Kikuchi JSasaki TMiyamoto KHashimoto T(2000)Delay-optimal wiring plan for the microprocessor of high performance computing machinesProceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)10.1109/ASPDAC.2000.835108(265-270)Online publication date: 2000
https://doi.org/10.1109/ASPDAC.2000.835108

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Super-scalar processor design

A unified processor architecture for RISC & VLIW DSP

A RISC processor for high-speed execution of genetic algorithms