research-article

Universal logic modules based on double-gate carbon nanotube transistors

Authors:

Andrew Zukoski,

Kartik MohanramAuthors Info & Claims

DAC '11: Proceedings of the 48th Design Automation Conference

Pages 884 - 889

https://doi.org/10.1145/2024724.2024921

Published: 05 June 2011 Publication History

Abstract

Double-gate carbon nanotube field-effect transistors (DG-CNT-FETs) can be controlled in the field to be either n-type or p-type through an extra polarity gate. This results in an embedded XOR behavior, which has inspired several novel circuit designs and architectures. This work makes the following contributions. First, we propose an accurate and efficient semi-classical modeling approach to realize the first SPICE-compatible model for circuit design and optimization of DG-CNTFETs. Second, we design and optimize universal logic modules (ULMs) in two circuit styles based on DG-CNTFETs. The proposed ULMs can leverage the full potential of the embedded XOR through the FPGA-centric lookup table optimization flow. Further, we demonstrate that DG-CNTFET ULMs in the double pass-transistor logic style, which inherently produces dual-rail outputs with balanced delay, are faster than DG-CNTFET circuits in the conventional single-rail static logic style that relies on explicit input inversion. On average across 12 benchmarks, the proposed dual-rail ULMs outperform the best DG-CNTFET fabrics based on tiling patterns by 37%, 12%, and 33% in area, delay, and total power, respectively.

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Cited By

Rahin AKadivarian ARahin V(2022)Design of a Full Swing 20-Transistors Full Adder Cell based on CNTFET with High Speed and Low PDP2022 30th International Conference on Electrical Engineering (ICEE)10.1109/ICEE55646.2022.9827050(546-550)Online publication date: 17-May-2022
https://doi.org/10.1109/ICEE55646.2022.9827050
Snelgrove AGaillardon P(2022)Programmable logic elements using multigate ambipolar transistors2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS54261.2022.9770137(112-117)Online publication date: 6-Apr-2022
https://doi.org/10.1109/DDECS54261.2022.9770137
Hu XAbraham AIncorvia JFriedman J(2021)Hybrid Pass Transistor Logic With Ambipolar TransistorsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.303404268:1(301-310)Online publication date: Jan-2021
https://doi.org/10.1109/TCSI.2020.3034042
Show More Cited By

Index Terms

Universal logic modules based on double-gate carbon nanotube transistors
1. Hardware
  1. Emerging technologies

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Published In

cover image ACM Conferences

DAC '11: Proceedings of the 48th Design Automation Conference

June 2011

1055 pages

ISBN:9781450306362

DOI:10.1145/2024724

General Chair:
Leon Stok
IBM Corp., Hopewell Jct., NY
,
Program Chairs:
Nikil Dutt
Univ. of California, Irvine, CA
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE Council on Electronic Design Automation (CEDA)

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 June 2011

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DAC '11

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DAC '11: The 48th Annual Design Automation Conference 2011

June 5 - 10, 2011

California, San Diego

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Rahin AKadivarian ARahin V(2022)Design of a Full Swing 20-Transistors Full Adder Cell based on CNTFET with High Speed and Low PDP2022 30th International Conference on Electrical Engineering (ICEE)10.1109/ICEE55646.2022.9827050(546-550)Online publication date: 17-May-2022
https://doi.org/10.1109/ICEE55646.2022.9827050
Snelgrove AGaillardon P(2022)Programmable logic elements using multigate ambipolar transistors2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS54261.2022.9770137(112-117)Online publication date: 6-Apr-2022
https://doi.org/10.1109/DDECS54261.2022.9770137
Hu XAbraham AIncorvia JFriedman J(2021)Hybrid Pass Transistor Logic With Ambipolar TransistorsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2020.303404268:1(301-310)Online publication date: Jan-2021
https://doi.org/10.1109/TCSI.2020.3034042
Reuter MPfau JKrauss TMoradinasab MSchwalke UBecker JHofmann K(2020)Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)10.1109/LASCAS45839.2020.9069043(1-4)Online publication date: Feb-2020
https://doi.org/10.1109/LASCAS45839.2020.9069043
Reuter MKrauss TMoradinasab MPfau JSchwalke UBecker JHofmann K(2019)From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)10.1109/APCCAS47518.2019.8953083(113-116)Online publication date: Nov-2019
https://doi.org/10.1109/APCCAS47518.2019.8953083
Saiphani Kumar GSingh ARaj B(2018)Design and analysis of a gate-all-around CNTFET-based SRAM cellJournal of Computational Electronics10.1007/s10825-017-1056-x17:1(138-145)Online publication date: 1-Mar-2018
https://dl.acm.org/doi/10.1007/s10825-017-1056-x
Raitza MKumar AVölp MWalter DTrommer JMikolajick TWeber W(2017)Exploiting transistor-level reconfiguration to optimize combinational circuitsProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130460(338-343)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130460
Raitza MKumar AVolp MWalter DTrommer JMikolajick TWeber W(2017)Exploiting transistor-level reconfiguration to optimize combinational circuitsDesign, Automation & Test in Europe Conference & Exhibition (DATE), 201710.23919/DATE.2017.7927013(338-343)Online publication date: Mar-2017
https://doi.org/10.23919/DATE.2017.7927013
Ghabri HBen Aissa DSamet HKachouri A(2016)Performance evaluation of reconfigurable ALU based on DG-CNTFET transistors2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)10.1109/STA.2016.7952102(142-146)Online publication date: Dec-2016
https://doi.org/10.1109/STA.2016.7952102
Ghabri HBen Issa DSamet H(2016)Reconfigurable circuits design based on DG-CNTFET transistors2016 13th International Multi-Conference on Systems, Signals & Devices (SSD)10.1109/SSD.2016.7473717(677-680)Online publication date: Mar-2016
https://doi.org/10.1109/SSD.2016.7473717
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