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Test set enrichment using a probabilistic fault model and the theory of output deviations

Authors:

Krishnendu Chakrabarty,

Michael GoesselAuthors Info & Claims

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

Pages 1270 - 1275

Published: 06 March 2006 Publication History

Abstract

We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theory of output deviations, can be used to supplement tests for classical fault models, thereby increasing test quality and reducing the probability of test escape. Output deviations can also be used for test selection, whereby the most effective test patterns can be selected from large test sets during time-constrained and high-volume production testing. Experimental results are presented to evaluate the effectiveness of patterns with high output deviations for the single stuck-at and bridging fault models.

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Cited By

Lingasubramanian KBhanja SZhou HMacii EYan ZMassoud Y(2007)Probabilistic maximum error modeling for unreliable logic circuitsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228842(223-226)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228842

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Published In

cover image Guide Proceedings

DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

March 2006

1390 pages

ISBN:3981080106

General Chair:
Georges Gielen
KU Leuven, BE

Sponsors

EDAA: European Design Automation Association
The EDA Consortium
IEEE-CS\DATC: The IEEE Computer Society

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;

Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

Lingasubramanian KBhanja SZhou HMacii EYan ZMassoud Y(2007)Probabilistic maximum error modeling for unreliable logic circuitsProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228842(223-226)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228842

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