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10.1109/ETS.2005.27guideproceedingsArticle/Chapter ViewAbstractPublication PagesConference Proceedingsacm-pubtype
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Logic Circuits Testing for Transient Faults

Published: 22 May 2005 Publication History

Abstract

Transient faults are becoming an increasingly serious concern for logic circuits. They can be caused by thermal neutrons, present at all altitudes, and by other types of ionizing radiation, especially in aerospace applications and nuclear engineering. In this paper we examine issues related to detection of transient errors. The difficulty in testing for transient errors is that they are not always present. Test vectors need to be repeated a number of times in order to detect a fault. We show how to compute a measure for the detectability of transient faults with respect to specific test vectors. This is done using a matrix-based gate-fault model known as the probabilistic transfer matrix model. Using this detectability measure we derive methods to generate multisets of tests to verify probability distributions of faults and detect abnormalities in circuit behavior. Applications of this method include detection of increased atmospheric radiation in terms of its impact on circuits, and testing for process variation that increases the susceptibility of a circuit to transient errors.

Cited By

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  • (2008)Probabilistic transfer matrices in symbolic reliability analysis of logic circuitsACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767413:1(1-35)Online publication date: 6-Feb-2008
  • (2006)Test set enrichment using a probabilistic fault model and the theory of output deviationsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131832(1270-1275)Online publication date: 6-Mar-2006
  • (2006)Software based fault toleranceUbiquity10.1145/1149633.11479952006:July(1-1)Online publication date: 1-Jul-2006

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  1. Logic Circuits Testing for Transient Faults

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          cover image Guide Proceedings
          ETS '05: Proceedings of the 10th IEEE European Symposium on Test
          May 2005
          207 pages
          ISBN:0769523412

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          IEEE Computer Society

          United States

          Publication History

          Published: 22 May 2005

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          Cited By

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          • (2008)Probabilistic transfer matrices in symbolic reliability analysis of logic circuitsACM Transactions on Design Automation of Electronic Systems10.1145/1297666.129767413:1(1-35)Online publication date: 6-Feb-2008
          • (2006)Test set enrichment using a probabilistic fault model and the theory of output deviationsProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131832(1270-1275)Online publication date: 6-Mar-2006
          • (2006)Software based fault toleranceUbiquity10.1145/1149633.11479952006:July(1-1)Online publication date: 1-Jul-2006

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