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Layout-aware pseudo-functional testing for critical paths considering power supply noise effects

Published: 08 March 2010 Publication History

Abstract

When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of the circuits. In this paper, we propose novel layout-aware pseudo-functional testing techniques to tackle the above problem. Firstly, by taking the circuit layout information into account, functional constraints related to delay faults on critical paths are extracted. Then, we generate functionally-reachable test cubes for every true critical path in the circuit. Finally, we fill the don't-care bits in the test cubes to maximize power supply noises on critical paths under the consideration of functional constraints. The effectiveness of the proposed methodology is verified with large ISCAS'89 benchmark circuits.

References

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Cited By

View all
  • (2011)Pseudo-functional testing for small delay defects considering power supply noise effectsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132333(34-39)Online publication date: 7-Nov-2011
  • (2010)A scalable quantitative measure of IR-drop effects for scan pattern generationProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133461(162-167)Online publication date: 7-Nov-2010
  • (2010)Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133460(155-161)Online publication date: 7-Nov-2010

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Information

Published In

cover image ACM Conferences
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
March 2010
1868 pages
ISBN:9783981080162

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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  • Research-article

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DATE '10
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '10: Design, Automation and Test in Europe
March 8 - 12, 2010
Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2011)Pseudo-functional testing for small delay defects considering power supply noise effectsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132333(34-39)Online publication date: 7-Nov-2011
  • (2010)A scalable quantitative measure of IR-drop effects for scan pattern generationProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133461(162-167)Online publication date: 7-Nov-2010
  • (2010)Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133460(155-161)Online publication date: 7-Nov-2010

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