Article

A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits

Authors:

Chandra Tirumurti,

Sandip Kundu,

Susmita Sur-Kolay,

Yi-Shing ChangAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

Page 21078

Published: 16 February 2004 Publication History

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Abstract

Power density of high-end microprocessors has been increasing by approximately 80% per technology generation, while the voltage is scaling by a factor of 0.8. This leads to 225% increase in current per unit area in successive generation of technologies. The cost of maintaining the same IR drop becomes too high. This leads to compromise in power delivery and power grid becomes a performance limiter. Traditional performance related test techniques with transition and path delay fault models focus on testing the logic but not the power delivery. In this paper we view power grid as performance limiter and develop a fault model to address the problem of vector generation for delay faults arising out of power delivery problems. A fault extraction methodology applied to a microprocessor design block is explained.

References

[1]

{1} S. T. Zachariah, Yi-Shing Chang, S. Kundu, C. Tirumurti, "On modeling Cross-talk Faults", Design, Automation and Test in Europe, pp. 490-495, March 2003.

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[2]

{2} Angela Krstic, Yi-Min Jiang and Kwang-Ting Cheng, "Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 3, March 2001.

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Jakushokas RFriedman EBrunvard EStevens KCavallaro JZhang T(2012)Link breaking methodologyProceedings of the great lakes symposium on VLSI10.1145/2206781.2206814(129-134)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206814
Yuan FLiu XXu QPhillips JHu AGraeb H(2011)Pseudo-functional testing for small delay defects considering power supply noise effectsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132333(34-39)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132333
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A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuits

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DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 2

February 2004

606 pages

ISBN:0769520855

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IEEE Computer Society

United States

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Published: 16 February 2004

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February 16 - 20, 2004

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Jakushokas RFriedman EBrunvard EStevens KCavallaro JZhang T(2012)Link breaking methodologyProceedings of the great lakes symposium on VLSI10.1145/2206781.2206814(129-134)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206814
Yuan FLiu XXu QPhillips JHu AGraeb H(2011)Pseudo-functional testing for small delay defects considering power supply noise effectsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132333(34-39)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132333
Gao MLisherness PCheng K(2011)Post-silicon bug detection for variation induced electrical bugsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950877(273-278)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950877
Voicu GEnachescu MCotofana S(2011)Towards "zero-energy" using NEMFET-based power management for 3D hybrid stacked ICsProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures10.1109/NANOARCH.2011.5941505(203-209)Online publication date: 8-Jun-2011
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Mu SWang YYang HChao MChen STseng CTsai TScheffer LPhillips JHu A(2010)Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133460(155-161)Online publication date: 7-Nov-2010
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Peng KHuang YGuo RCheng WTehranipoor MLin Y(2010)Emulating and diagnosing IR-drop by using dynamic SDFProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899842(511-516)Online publication date: 18-Jan-2010
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Liu XZhang YYuan FXu QDe Micheli GAl-Hashimi BMueller WMacii E(2010)Layout-aware pseudo-functional testing for critical paths considering power supply noise effectsProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871271(1432-1437)Online publication date: 8-Mar-2010
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Fu XLi HHu YLi XKyung CChoi KHa S(2008)Robust test generation for power supply noise induced path delay faultsProceedings of the 2008 Asia and South Pacific Design Automation Conference10.5555/1356802.1356962(659-662)Online publication date: 21-Jan-2008
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Lee JNarayan SKapralos MTehranipoor MSciuto D(2008)Layout-aware, IR-drop tolerant transition fault pattern generationProceedings of the conference on Design, automation and test in Europe10.1145/1403375.1403661(1172-1177)Online publication date: 10-Mar-2008
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Polian ICzutro AKundu SBecker B(2007)Power Droop TestingIEEE Design & Test10.1109/MDT.2007.7724:3(276-284)Online publication date: 1-May-2007
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LCNT-an approach to minimize leakage power in CMOS integrated circuits

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