Triplet-based topology for on-chip networks

Most CMPs use on-chip network to connect cores and tend to integrate more simple cores on a single die. As the number of cores increases, on-chip network will play an important role in the performance of future CMPs. Due to the tradeoff between the performance and area constraint in on-chip network designs, we propose the use of triplet-based topology in on-chip interconnection networks and demonstrate how a 9-node triplet-based topology can be mapped to on-chip network. By using group-caching protocol to exploit traffic locality, triplet-based topology achieve lower latency and energy consumption than 2D-MESH. We run multithreaded commercial benchmarks on multi-core simulator GEMS to generate practical traffics and simulate these traffics on network simulator Garnet. Our experiment results show that triplet-based network can increase the work-related throughput by 3%-11% and reduce average network latency by 24%-32% compared with 2D-MESH, with the router energy consumption reduced by 13%-16% and the link energy consumption reduced by 14%-16%.