Article

SUNMAP: a tool for automatic topology selection and generation for NoCs

Authors:

Srinivasan Murali,

Giovanni De MicheliAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 914 - 919

https://doi.org/10.1145/996566.996809

Published: 07 June 2004 Publication History

Abstract

Increasing communication demands of processor and memory cores in Systems on Chips (SoCs) necessitate the use of Networks on Chip (NoC) to interconnect the cores. An important phase in the design of NoCs is he mapping of cores onto the most suitable opology for a given application. In this paper, we present SUNMAP a tool for automatically selecting he best topology for a given application and producing a mapping of cores onto that topology. SUNMAP explores various design objectives such as minimizing average communication delay, area, power dissipation subject to bandwidth and area constraints. The tool supports different routing functions (dimension ordered, minimum-path, traffic splitting) and uses floorplanning information early in the topology selection process to provide feasible mappings. The network components of the chosen NoC are automatically generated using cycle-accurate SystemC soft macros from X-pipes architecture. SUNMAP automates NoC selection and generation, bridging an important design gap in building NoCs. Several experimental case studies are presented in the paper, which show the rich design space exploration capabilities of SUNMAP.

References

[1]

M. Sgroi et al., " Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design", in Proc. Design Automation Conference, 2001.

Digital Library

[2]

L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, pp. 70--78, Jan. 2002.

Digital Library

[3]

P. Guerrier, A. Greiner, "A generic architecture for on-chip packet switched interconnections", DATE 2000, pp. 250--256, March 2000.

Digital Library

[4]

S. Kumar et al., "A network on chip architecture and design methodology", ISVLSI 2002, pp.105--112, 2002.

[5]

E. Rijpkema et al., "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip", DATE 2003, pp. 350--355, Mar 2003.

Digital Library

[6]

F. Karim et al., "On-chip communication architecture for OC-768 network processors", Design Automation Conference, June 2001.

Digital Library

[7]

X. Zhu, S. Malik, "A Hierarchical Modeling Framework for On-Chip Communication Architectures", ICCD 2002, pp. 663--671, Nov 2002.

Digital Library

[8]

L. Jian, et. al, "aSOC: A Scalable, Single-Chip communications Architecture", PACT 2000, Oct. 2000, pp. 37--46.

Digital Library

[9]

D.Siguenza-Tortosa, J. Nurmi, " Proteo: A New Approach to Network-on-Chip", in CSN 02, Sep. 2002.

[10]

S. J. Lee et al., "An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip", ISSCC 2003, Feb. 2003.

[11]

A. Jantsch, H. Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003.

Digital Library

[12]

S. J. Krolikoski, et. al, "Methodology and Technology for Virtual Component Driven Hardware/Software Co-Design on the System-Level", ISCAS 99, pp. 456--459, June 1999.

[13]

E. B. Van der Tol, E. G. T. Jaspers, "Mapping of MPEG-4 Decoding on a Flexible Architecture Platform", SPIE 2002, pp. 1--13, Jan, 2002.

[14]

A. Pinto et. al, "Efficient Synthesis of Networks on Chip", ICCD 2003, pp. 146--150, Oct 2003.

Digital Library

[15]

W. H. Ho, T. M. Pinkston, "A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns", HPCA 2003, pp. 377--388, Feb 2003.

Digital Library

[16]

J. Hu, R. Marculescu, "Energy-Aware Mapping for Tile-based NOC Architectures Under Performance Constraints", ASP-DAC 2003, Jan 2003.

Digital Library

[17]

"xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs", pp. 536--539, ICCD, 2003.

Digital Library

[18]

"xpipesCompiler: A Tool For Instantiating Application Specific Networks on Chips", Vol. 2, pp. 20884, DATE 2004.

[19]

"Bandwidth Constrained Mapping of Cores onto NoC Architectures", Vol. 2, pp. 20896, DATE 2004.

[20]

J. G. Kim, Y. D. Kim, "A linear programming-based algorithm for floorplanning in VLSI design ", IEEE Transactions on CAD, pp. 584--592, Vol. 22, Issue: 5, May 2003.

Digital Library

[21]

N. Sherwani, "Algorithms for VLSI Physical Design Automation". Kluwer Academic Publishers, 1995.

Digital Library

[22]

H. S Wang et al., "Orion: A Power-Performance Simulator for Interconnection Networks", MICRO, Nov. 2002.

Digital Library

[23]

R. Ho, K. Mai, and M. Horowitz, "The Future of Wires", Proceedings of the IEEE, pp. 490--504, April 2001.

Cited By

Hanson ELi SZhou GCheng FWang YBose RLi HChen Y(2023)Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AIProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614278(972-985)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614278
Mazumdar SScionti AZuckerman SPortero A(2023)NoC-based hardware software co-design framework for dataflow thread managementThe Journal of Supercomputing10.1007/s11227-023-05335-879:16(17983-18020)Online publication date: 11-May-2023
https://dl.acm.org/doi/10.1007/s11227-023-05335-8
Li FWang YLiu CLi HLi XBolchini CO'Connor IVerbauwhede IWille R(2022)NoCeptionProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540084(1035-1040)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540084
Show More Cited By

Index Terms

SUNMAP: a tool for automatic topology selection and generation for NoCs
1. Hardware
  1. Communication hardware, interfaces and storage
    1. Buses and high-speed links
  2. Hardware validation

Recommendations

Application specific NoC design
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings

Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for high-end wireless communications applications. The heterogeneous nature of on-chip cores, and the ...
Synthesis of networks on chips for 3D systems on chips
ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity. ...
A modular simulation framework for architectural exploration of on-chip interconnection networks
CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prevent time consuming design changes late in the design flow, we propose the ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 June 2004

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

DAC04

Sponsor:

DAC04: The 41st Annual Design Automation Conference 2004

June 7 - 11, 2004

CA, San Diego, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

199
Total Citations
View Citations
1,031
Total Downloads

Downloads (Last 12 months)22
Downloads (Last 6 weeks)1

Reflects downloads up to 01 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Hanson ELi SZhou GCheng FWang YBose RLi HChen Y(2023)Si-Kintsugi: Towards Recovering Golden-Like Performance of Defective Many-Core Spatial Architectures for AIProceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3613424.3614278(972-985)Online publication date: 28-Oct-2023
https://dl.acm.org/doi/10.1145/3613424.3614278
Mazumdar SScionti AZuckerman SPortero A(2023)NoC-based hardware software co-design framework for dataflow thread managementThe Journal of Supercomputing10.1007/s11227-023-05335-879:16(17983-18020)Online publication date: 11-May-2023
https://dl.acm.org/doi/10.1007/s11227-023-05335-8
Li FWang YLiu CLi HLi XBolchini CO'Connor IVerbauwhede IWille R(2022)NoCeptionProceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe10.5555/3539845.3540084(1035-1040)Online publication date: 14-Mar-2022
https://dl.acm.org/doi/10.5555/3539845.3540084
Li FWang YLiu CLi HLi X(2022)NoCeption: A Fast PPA Prediction Framework for Network-on-Chips Using Graph Neural Network2022 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE54114.2022.9774525(1035-1040)Online publication date: 14-Mar-2022
https://doi.org/10.23919/DATE54114.2022.9774525
Kadri NKoudil M(2022)Multi-objective biogeography-based optimization and reinforcement learning hybridization for network-on chip reliability improvementJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.11.005161:C(20-36)Online publication date: 1-Mar-2022
https://dl.acm.org/doi/10.1016/j.jpdc.2021.11.005
Ding HQian JZhao LZhai Z(2021)A mathematical programming method for constructing the shortest interconnection VLSI arraysIntegration, the VLSI Journal10.1016/j.vlsi.2021.07.00481:C(167-174)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.vlsi.2021.07.004
Krishna TKwon HParashar APellauer MSamajdar A(2020)Data Orchestration in Deep Learning AcceleratorsSynthesis Lectures on Computer Architecture10.2200/S01015ED1V01Y202005CAC05215:3(1-164)Online publication date: 17-Aug-2020
https://doi.org/10.2200/S01015ED1V01Y202005CAC052
Weng JLiu SDadu VWang ZShah PNowatzki TMartínez JDuato JEeckhout L(2020)DSAGENProceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00032(268-281)Online publication date: 30-May-2020
https://dl.acm.org/doi/10.1109/ISCA45697.2020.00032
Morgan AHassan AEl-Kharashi MTawfik A(2020) NoC 2 : An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems IEEE Access10.1109/ACCESS.2020.30306068(185992-186011)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3030606
Zhang YRucker AVilim MPrabhakar RHwang WOlukotun KManne SHunter HAltman E(2019)Scalable interconnects for reconfigurable spatial architecturesProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322249(615-628)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322249
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents