Article

Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

Authors:

Elana Granston,

Eric Stotzer,

Joe ZbiciakAuthors Info & Claims

LCTES '01: Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems

Pages 138 - 144

https://doi.org/10.1145/384197.384216

Published: 01 August 2001 Publication History

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Abstract

The TMS320C6000 architecture is a leading family of Digital Signal Processors (DSPs). To achieve peak performance, this VLIW architecture relies heavily on software pipelining. Traditionally, software pipelining has been restricted to regular (FOR) loops. More recently, software pipelining has been extended to irregular (WHILE) loops, but only on architectures that provide special-purpose hardware such as rotating (predicate and general-purpose) register files, specific instructions for filling/draining software pipelined loops, and possibly hardware support for speculative code motion. In contrast, the TMS320C6000 family has a limited, static register file and no specialized hardware beyond the ability to predicate instructions using a few static registers. In this paper, we describe our experience extending a production compiler for the TMS320C6000 family to software pipeline irregular loops. We discuss our technique for preprocessing irregular loops so that they can be handled by the existing software pipeliner. Our approach is much simpler than previous approaches and works very well in the presence of the DSP applications and the target architecture which characterize our environment. With this optimization, we achieve impressive speedups on several key DSP and non-DSP algorithms.

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Cited By

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Zhuge QXue CQiu MHu JSha E(2008)Timing optimization via nest-loop pipelining considering code sizeMicroprocessors & Microsystems10.1016/j.micpro.2008.02.00232:7(351-363)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1016/j.micpro.2008.02.002
Hatanaka ABagherzadeh N(2007)A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template2007 IEEE International Parallel and Distributed Processing Symposium10.1109/IPDPS.2007.370371(1-8)Online publication date: Mar-2007
https://doi.org/10.1109/IPDPS.2007.370371
Chabini NWolf W(2007)Reducing the Code Size of Retimed Software Loops under Timing and Resource ConstraintsEmbedded System Design: Topics, Techniques and Trends10.1007/978-0-387-72258-0_22(255-268)Online publication date: 2007
https://doi.org/10.1007/978-0-387-72258-0_22
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Index Terms

Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture
1. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Published In

LCTES '01: Proceedings of the ACM SIGPLAN workshop on Languages, compilers and tools for embedded systems

August 2001

250 pages

ISBN:1581134258

DOI:10.1145/384197

Chairmen:
Seongsoo Hong
Snow Bird, UT
,
Santosh Pande
Snow Bird, UT

ACM SIGPLAN Notices Volume 36, Issue 8
Aug. 2001
245 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/384196
Chairman:
Ron K. Cytron
Washington Univ., St. Louis, MO
,
Editor:
Cindy Norris
Appalachian State Univ., Boone, NC
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 2001

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LCTES01: Workshop on Languages, Compilers and Tools for Embedded Systems 2001 ( co-located with PLDI 2001 )

Utah, Snow Bird, USA

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Cited By

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Zhuge QXue CQiu MHu JSha E(2008)Timing optimization via nest-loop pipelining considering code sizeMicroprocessors & Microsystems10.1016/j.micpro.2008.02.00232:7(351-363)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1016/j.micpro.2008.02.002
Hatanaka ABagherzadeh N(2007)A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template2007 IEEE International Parallel and Distributed Processing Symposium10.1109/IPDPS.2007.370371(1-8)Online publication date: Mar-2007
https://doi.org/10.1109/IPDPS.2007.370371
Chabini NWolf W(2007)Reducing the Code Size of Retimed Software Loops under Timing and Resource ConstraintsEmbedded System Design: Topics, Techniques and Trends10.1007/978-0-387-72258-0_22(255-268)Online publication date: 2007
https://doi.org/10.1007/978-0-387-72258-0_22
Zhuge QXue CShao ZLiu MQiu MSha E(2006)Design optimization and space minimization considering timing and code size via retiming and unfoldingMicroprocessors and Microsystems10.1016/j.micpro.2005.11.00230:4(173-183)Online publication date: Jun-2006
https://doi.org/10.1016/j.micpro.2005.11.002

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Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

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