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Code generation schema for modulo scheduled loops

Authors:

B. Ramakrishna Rau,

Michael S. Schlansker,

P. P. TirumalaiAuthors Info & Claims

MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture

Pages 158 - 169

Published: 10 December 1992 Publication History

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Cited By

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Wei HYu JYu HGao GMoshovos ASteffan GHazelwood KKaeli D(2010)Minimizing communication in rate-optimal software pipelining for stream programsProceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1772954.1772984(210-217)Online publication date: 24-Apr-2010
https://dl.acm.org/doi/10.1145/1772954.1772984
Udupa AGovindarajan RThazhuthaveetil M(2009)Synergistic execution of stream programs on multicores with acceleratorsACM SIGPLAN Notices10.1145/1543136.154246644:7(99-108)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1543136.1542466
Udupa AGovindarajan RThazhuthaveetil MKirsch CKandemir M(2009)Synergistic execution of stream programs on multicores with acceleratorsProceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1542452.1542466(99-108)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1542452.1542466
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Information & Contributors

Information

Published In

MICRO 25: Proceedings of the 25th annual international symposium on Microarchitecture

December 1992

301 pages

ISBN:0818631759

Chairman:
Wen-mei Hwu

ACM SIGMICRO Newsletter Volume 23, Issue 1-2
Dec. 1992
300 pages
ISSN:1050-916X
DOI:10.1145/144965
Editor:
Wen-mei Hwu
Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 10 December 1992

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Conference

MICRO92

Sponsor:

SIGMICRO
IEEE-CS

MICRO92: 25th Annual International Symposium on Microarchitecture

December 1 - 4, 1992

Oregon, Portland, USA

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Wei HYu JYu HGao GMoshovos ASteffan GHazelwood KKaeli D(2010)Minimizing communication in rate-optimal software pipelining for stream programsProceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization10.1145/1772954.1772984(210-217)Online publication date: 24-Apr-2010
https://dl.acm.org/doi/10.1145/1772954.1772984
Udupa AGovindarajan RThazhuthaveetil M(2009)Synergistic execution of stream programs on multicores with acceleratorsACM SIGPLAN Notices10.1145/1543136.154246644:7(99-108)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1543136.1542466
Udupa AGovindarajan RThazhuthaveetil MKirsch CKandemir M(2009)Synergistic execution of stream programs on multicores with acceleratorsProceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1542452.1542466(99-108)Online publication date: 19-Jun-2009
https://dl.acm.org/doi/10.1145/1542452.1542466
Udupa AGovindarajan RThazhuthaveetil M(2009)Software Pipelined Execution of Stream Programs on GPUsProceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization10.1109/CGO.2009.20(200-209)Online publication date: 22-Mar-2009
https://dl.acm.org/doi/10.1109/CGO.2009.20
Clark NHormati AMahlke S(2008)VEALACM SIGARCH Computer Architecture News10.1145/1394608.138215536:3(389-400)Online publication date: 1-Jun-2008
https://dl.acm.org/doi/10.1145/1394608.1382155
Kudlur MMahlke S(2008)Orchestrating the execution of stream programs on multicore platformsACM SIGPLAN Notices10.1145/1379022.137559643:6(114-124)Online publication date: 7-Jun-2008
https://dl.acm.org/doi/10.1145/1379022.1375596
Kudlur MMahlke SGupta RAmarasinghe S(2008)Orchestrating the execution of stream programs on multicore platformsProceedings of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/1375581.1375596(114-124)Online publication date: 7-Jun-2008
https://dl.acm.org/doi/10.1145/1375581.1375596
Clark NHormati AMahlke S(2008)VEALProceedings of the 35th Annual International Symposium on Computer Architecture10.1109/ISCA.2008.33(389-400)Online publication date: 21-Jun-2008
https://dl.acm.org/doi/10.1109/ISCA.2008.33
Zhuge QXue CQiu MHu JSha E(2008)Timing optimization via nest-loop pipelining considering code sizeMicroprocessors & Microsystems10.1016/j.micpro.2008.02.00232:7(351-363)Online publication date: 1-Oct-2008
https://dl.acm.org/doi/10.1016/j.micpro.2008.02.002
Larsen SRabbah RAmarasinghe S(2005)Exploiting Vector Parallelism in Software Pipelined LoopsProceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2005.20(119-129)Online publication date: 12-Nov-2005
https://dl.acm.org/doi/10.1109/MICRO.2005.20
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