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Sentinel scheduling for VLIW and superscalar processors

Authors:

Michael S. SchlanskerAuthors Info & Claims

ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

Pages 238 - 247

https://doi.org/10.1145/143365.143529

Published: 01 September 1992 Publication History

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Abstract

Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to accurately detect and report all program execution errors at the time of occurrence. In this paper, a set of architectural features and compile-time scheduling support referred to as sentinel scheduling is introduced. Sentinel scheduling provides an effective framework for compiler-controlled speculative execution that accurately detects and reports all exceptions. Sentinel scheduling also supports speculative execution of store instructions by providing a store buffer which allows probationary entries. Experimental results show that sentinel scheduling is highly effective for a wide range of VLIW and superscalar processors.

References

[1]

B. R. Rau and C. D. Glaeser, "Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing," in Proceedings of the ~Oth Annual Workshop on Microprogrammin9 and Microarchitecture, pp. 183-198, October 1981.

Digital Library

Google Scholar

[2]

M. S. Lain, "Software pipehning: An effective scheduling technique for VLIW machines," in Proceedings of the A CM SIGPLAN 1988 Conference on Programming Language Design and Implementation, pp. 318-328, June 1988.

Digital Library

Google Scholar

[3]

A. Aiken and A. Nicolau, "Optimal loop paraJlelization," in Proceedings o} the A CM SIGPLAN 1988 Conference on Programming Language Design and Implementation, pp. 308-317, June 1988.

Digital Library

Google Scholar

[4]

B. R. Rau, D. W. L. Yen, W. Yen, and R. A. Towle, "The Cydra 5 departmental supercomputer," IEEE Computer, pp. 12-35, January 1989.

Digital Library

Google Scholar

[5]

P. Y. T. Hsu and E. S. Davidson, "Highly concurrent scMar processing," in Proceedings of the 13th International Symposium on Computer Architecture, pp. 386- 395, June 1986.

Digital Library

Google Scholar

[6]

M. D. Smith, M. S. Lain, and M. A. Horowitz, "Boosting beyond static scheduling in a superscMar processor,'' in Proceedings of the 17th International Symposium on Computer Architecture, pp. 344-354, May 1990.

Digital Library

Google Scholar

[7]

P. Tirumalai, M. Lee, and M. Schlansker, "Parallelization of loops with exits on pipelined architectures," in Proceedings of Supercomputing '90, November 1990.

Digital Library

Google Scholar

[8]

P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Warter, and W. W. Hwu, "IMPACT: An architectural framework for multiple-instruction-issue processors," in Proceedings of the 18th International Symposium on Computer Architecture, pp. 266-275, May 1991.

Digital Library

Google Scholar

[9]

J. A. Fisher, "Trace scheduling: A technique for global microcode compaction," IEEE Transactions on Computers, vol. c-30, pp. 478-490, July 1981.

Digital Library

Google Scholar

[10]

K. Ebcioglu, "A compilation technique for software pipelining of loops with conditional jumps," in Proceedings of the ~Oth Annual Workshop on Microprogramruing and Microarchitecture, pp. 69-79, December 1987.

Digital Library

Google Scholar

[11]

R. P. Colwell, R. P. Nix, J. J. O'Donnell, D. B. Papworth, and P. K. Rodman, "A VLIW architecture for a trace scheduling compiler," in Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 180-192, April 1987.

Crossref

Google Scholar

[12]

A. Aho, R. Sethi, and J. Ullman, Compilers: Principles, Techniques, and Tools. Reading, MA: Addison-Wesley, 1986.

Digital Library

Google Scholar

[13]

S. A. Mahlke, W. Y. Chen, W. W. Itwu, B. R. Rau, and M. S. Schlansker, "Exception recovery for systems with compiler-controlled speculative execution," tech. rep., Center for Reh~ble and High-Performance Computing, University of Illinois, Urbana, IL, in preparation 1992.

Google Scholar

[14]

W. M. Johnson, Superscalar Microprocessor Design. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1991.

Google Scholar

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Alshboul MElnawawy HElkhouly RKimura KTuck JSolihin Y(2019)Efficient Checkpointing with Recompute Scheme for Non-volatile Main MemoryACM Transactions on Architecture and Code Optimization10.1145/332309116:2(1-27)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3323091
Liu QIzraelevitz JLee SScott MNoh SJung COskin MInoue K(2018)iDOProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00029(258-270)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00029
Alshboul MTuck JSolihin Y(2018)Lazy persistencyProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00044(439-451)Online publication date: 2-Jun-2018
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Index Terms

Sentinel scheduling for VLIW and superscalar processors
1. Software and its engineering
  1. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Scheduling
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Scheduling algorithms
    2. Online algorithms
      1. Online learning algorithms
        Scheduling algorithms
  2. Theory and algorithms for application domains
    1. Machine learning theory
      1. Reinforcement learning
        Sequential decision making

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Sentinel scheduling: a model for compiler-controlled speculative execution

Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to efficiently handle exceptions for speculative instructions. In this article, a set ...
Sentinel scheduling for VLIW and superscalar processors

Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to accurately detect and report all program execution errors at the time of ...
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Published In

ASPLOS V: Proceedings of the fifth international conference on Architectural support for programming languages and operating systems

September 1992

308 pages

ISBN:0897915348

DOI:10.1145/143365

Chairman:
Barry Flahive
Hewlett-Packard
,
Editor:
Richard L. Wexelblat

ACM SIGPLAN Notices Volume 27, Issue 9
Sept. 1992
278 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/143371
Editors:
Richard L. Wexelblat,
Barry Flahive
Hewlett-Packard
Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 September 1992

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ASPLOS92: 5th Conference on Architectural Support of Programming Languages & Operating Systems

October 12 - 15, 1992

Massachusetts, Boston, USA

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Alshboul MElnawawy HElkhouly RKimura KTuck JSolihin Y(2019)Efficient Checkpointing with Recompute Scheme for Non-volatile Main MemoryACM Transactions on Architecture and Code Optimization10.1145/332309116:2(1-27)Online publication date: 29-May-2019
https://dl.acm.org/doi/10.1145/3323091
Liu QIzraelevitz JLee SScott MNoh SJung COskin MInoue K(2018)iDOProceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture10.1109/MICRO.2018.00029(258-270)Online publication date: 20-Oct-2018
https://dl.acm.org/doi/10.1109/MICRO.2018.00029
Alshboul MTuck JSolihin Y(2018)Lazy persistencyProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00044(439-451)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00044
Tanasic IGelado IJorda MAyguade ENavarro NHunter HMoreno JEmer JSanchez D(2017)Efficient exception handling support for GPUsProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123950(109-122)Online publication date: 14-Oct-2017
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Chen GShen X(2016)Coherence-Free MultiviewProceedings of the 2016 International Conference on Supercomputing10.1145/2925426.2926277(1-13)Online publication date: 1-Jun-2016
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de Dinechin B(2014)Using the SSA-Form in a Code GeneratorCompiler Construction10.1007/978-3-642-54807-9_1(1-17)Online publication date: 2014
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Mitropoulou KPorpodas VCintra M(2014)DRIFT: Decoupled CompileR-Based Instruction-Level Fault-ToleranceLanguages and Compilers for Parallel Computing10.1007/978-3-319-09967-5_13(217-233)Online publication date: 1-Oct-2014
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de Kruijf MSankaralingam KJha S(2012)Static analysis and compiler design for idempotent processingACM SIGPLAN Notices10.1145/2345156.225412047:6(475-486)Online publication date: 11-Jun-2012
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de Kruijf MSankaralingam KJha SVitek JLin HTip F(2012)Static analysis and compiler design for idempotent processingProceedings of the 33rd ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/2254064.2254120(475-486)Online publication date: 11-Jun-2012
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Sentinel scheduling: a model for compiler-controlled speculative execution

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