Extended Instruction Exploration for Multiple-Issue Architectures
Article No.: 92, Pages 1 - 28
Abstract
In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for architectural enhancement, while issuing multiple instructions is a common approach for microarchitectural enhancement. The impact of combining both of these approaches in the same design is not well understood. While previous studies have shown that EI can potentially improve performance in some applications on certain multiple-issue architectures, the algorithms used to identify EI for multiple-issue architectures yield only limited performance improvement. This is because not all arithmetic operations are suited for EI for multiple-issue architectures. To explore the full potential of EI for multiple-issue architectures, two important factors need to be considered: (1) the execution performance of an application is dominated by critical (located on the critical path) and highly resource-contentious (i.e., having a high probability of being delayed during execution due to hardware resource limitations) operations, and (2) an operation may become critical and/or highly resource contentious after some operations are added to the EI. This article presents an EI exploration algorithm for multiple-issue architectures that focuses on these two factors. Simulation results show that the proposed algorithm outperforms previously published algorithms.
References
[1]
ALTERA CORP. 2004. Nios II Processor Reference Handbook. http://www.altera.com/literature/lit-nio2.jsp.
[2]
K. Atasu, L. Pozzi, and P. Ienne. 2003. Automatic application-specific instruction-set extensions under microarchitectural constraints. In Proceedings of the 40th Design Automation Conference (DAC). 256--261.
[3]
P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne. 2006. ISEGEN: An iterative improvement-based ISE generation technique for fast customization of processors. IEEE Trans. Integ. VLSI Syst. 14, 7, 754--762.
[4]
N. T. Clark, H. Zhong, K. Fan, S. Mahlke, K. Flautner, and V. Nieuwenhove. 2004. OptimoDE: Programmable accelerator engines through retargetable customization. In Proceedings of the Symposium on High Performance Chips (HotChips).
[5]
N. T. Clark, H. Zhong, and S. A. Mahlk. 2005. Automated custom instruction generation for domain-specific processor acceleration. IEEE Trans. Comput. 54, 10, 1258--1270.
[6]
G. David, M. A. Ertl, and A. Krall. 2001. A fast Java interpreter. In Proceedings of the Java Optimization Strategies for Embedded Systems Workshop (JOSES).
[7]
P. Faraboschi, G. Brown, J. A. Fisher, G. Desoli, and F. Homewood. 2000. LX: A technology platform for customizable VLIW embedded processing. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA). 203--213.
[8]
C. Galuzzi and K. Bertels. 2011. The instruction-set extension problem: A survey. ACM Trans. Reconfi. Technol. Syst. 18.
[9]
D. Goodwin and D. Petkov. 2003. Automatic generation of application specific processors. In Proceedings of the International Conference on Compilers Architectures and Synthesis for Embedded Systems (CASES). 137--147.
[10]
M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, and R. B. Brow. 2001. MiBench: A free, commercially representative embedded benchmark suite. In Proceedings of the IEEE 4th Annual Workshop on Workload Characterization (WWC). 3--14.
[11]
T. R. Halfhill. 2000. ARC cores encourages plug-ins. Microprocess. Rep. 14, 4, 42--44.
[12]
T. R. Halfhill. 2003a. MIPS embraces configurable technology. Microprocess. Rep.
[13]
T. R. Halfhill. 2003b. Tensilica's software makes hardware. Microprocess. Rep.
[14]
D. Jain, A. Kumar, L. Pozzi, and P. Ienne. 2004. Automatically customising VLIW architectures with coarse grained application-specific functional units. In Proceedings of the 8th International Workshop on Software and Compilers for Embedded Systems (SCOPES). 17--32.
[15]
C. Lattner. 2002. LLVM: An infrastructure for multi-stage optimization. Master's thesis. Computer Science Dept., University of Illinois at Urbana-Champaign, IL.
[16]
C. Liem, T. May, and P. Paulin. 1994. Instruction-set matching and selection for DSP and ASIP code generation. In Proceedings of the European Design and Test Conference (ED&TC). 31--37.
[17]
A. Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, and R. Guerrieri. 2003. A VLIW processor with reconfigurable instruction set for embedded applications. IEEE J. Solid-State Circuits. 38, 11, 1876--1886.
[18]
Y. S. Lü, L. Shen, L. Huang, Z. Y. Wang, and N. Xiao. 2008. Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. In Proceedings of the 45th Annual Design Automation Conference (DAC). 197--200.
[19]
L. Pozzi and P. Ienne. 2006. Automatic instruction set extension. In Customizable Embedded Processors, Morgan Kaufmann, San Mateo, CA.
[20]
L. Pozzi, K. Atasu, and P. Ienne. 2006. Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput.-Aid. Des. Integ. Circuits Syst. 25, 7, 1209--1229.
[21]
D. S. Rao and F. J. Kurdahi. 1992. Partitioning by regularity extraction. In Proceedings of the 29th Design Automation Conference (DAC). 235--238.
[22]
V. S. Reddy. 2006. Exploring VLIW ASIP design space using trimaran based framework. Master's thesis. Department of Computer Science and Engineering, Indian Institute of Technology Delhi.
[23]
M. A. R. Saghir, M. El-Majzoub, and P. Alk. 2007. Customizing the datapath and ISA of soft VLIW processors. In Proceedings of the 2nd International Conference an High Performance Embedded Architectures and Compilers (HiPEAC). Lecture Notes in Computer Science, vol. 4367, Spring, 276--290.
[24]
W. Stephan, T. V. As, and G. Brown. 2008. ρ-VEX: A reconfigurable and extensible softcore VLIW processor. In Proceedings of the IEEE International Conference on Field-Programmable Technologies (ICFPT). 369--372.
[25]
F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha. 2002. Synthesis of custom processors based on extensible platforms. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 641--648.
[26]
I. W. Wu, S.-C. Huang, C.-P. Chung, and J.-J. Shann. 2007. Instruction set extension generation with considering physical constraints. In Proceedings of the 2nd International Conference on High Performance Embedded Architecture and Compilers. Lecture Notes in Computer Science, vol. 4367, Springer-Verlag, Berlin Heidelberg, 291--305.
[27]
P. Yu and T. Mitra. 2007. Disjoint pattern enumeration for custom instructions identification. In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). 273--278.
Index Terms
- Extended Instruction Exploration for Multiple-Issue Architectures
Recommendations
A power-driven multiplication instruction-set design method for ASIPs
This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication ...
A high performance processor architecture for multimedia applications
In this paper, an efficient sub-word parallelism (SWP)-enabled Reduced instruction-set Computer (RISC) architecture is proposed. The proposed architecture can perform efficiently for both conventional and multimedia-oriented applications. Speed-up for ...
Increasing the instruction fetch rate via block-structured instruction set architectures
MICRO 29: Proceedings of the 29th annual ACM/IEEE international symposium on MicroarchitectureTo exploit larger amounts of instruction level parallelism, processors are being built with wider issue widths and larger numbers of functional units. Instruction fetch rate must also be increased in order to effectively exploit the performance ...
Comments
Please enable JavaScript to view thecomments powered by Disqus.Information & Contributors
Information
Published In
November 2014
647 pages
Copyright © 2014 ACM.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 10 March 2014
Accepted: 01 September 2013
Revised: 01 July 2013
Received: 01 September 2012
Published in TECS Volume 13, Issue 4
Check for updates
Author Tags
Qualifiers
- Research-article
- Research
- Refereed
Funding Sources
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 174Total Downloads
- Downloads (Last 12 months)3
- Downloads (Last 6 weeks)0
Reflects downloads up to 29 Nov 2024
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in