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Write performance improvement by hiding R drift latency in phase-change RAM

Published: 03 June 2012 Publication History

Abstract

Phase-change RAM (PRAM) is considered to be one of the most promising candidates to complement or replace DRAM in the near future. However, it is imperative to overcome the limitations of PRAM, especially, long write latency for its widespread applications. R drift latency occupies a significant portion in PRAM write latency thereby adversely affecting system performance. In this paper, we propose a novel method called write status holding register (WSHR) to reduce the write latency due to R drift latency. The WSHR allows for non-blocking accesses to PRAM during R drift latency thereby improving system performance. Our experiments with SPEC benchmarks show that the proposed WSHR gives 53.6%~0% performance improvements in the hybrid DRAM/PRAM main memory (256MB DRAM and 14nm PRAM).

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Cited By

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  • (2023)An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change MemoryIEEE Transactions on Computers10.1109/TC.2022.319707172:4(1150-1162)Online publication date: 1-Apr-2023
  • (2022)PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS55109.2022.00043(300-310)Online publication date: May-2022
  • (2019)Integration and Boost of a Read-Modify-Write Module in Phase Change Memory SystemIEEE Transactions on Computers10.1109/TC.2019.293382668:12(1772-1784)Online publication date: 1-Dec-2019
  • Show More Cited By

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    cover image ACM Conferences
    DAC '12: Proceedings of the 49th Annual Design Automation Conference
    June 2012
    1357 pages
    ISBN:9781450311991
    DOI:10.1145/2228360
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 03 June 2012

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    Author Tags

    1. R drift
    2. phase-change RAM
    3. write performance

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    DAC '12: The 49th Annual Design Automation Conference 2012
    June 3 - 7, 2012
    California, San Francisco

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    Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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    Cited By

    View all
    • (2023)An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change MemoryIEEE Transactions on Computers10.1109/TC.2022.319707172:4(1150-1162)Online publication date: 1-Apr-2023
    • (2022)PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis2022 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)10.1109/ISPASS55109.2022.00043(300-310)Online publication date: May-2022
    • (2019)Integration and Boost of a Read-Modify-Write Module in Phase Change Memory SystemIEEE Transactions on Computers10.1109/TC.2019.293382668:12(1772-1784)Online publication date: 1-Dec-2019
    • (2018)DyPhaseIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.276292137:9(1760-1773)Online publication date: 1-Sep-2018
    • (2017)CompEx++ACM Transactions on Architecture and Code Optimization10.1145/305044014:1(1-30)Online publication date: 14-Apr-2017
    • (2017)DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.6(41-46)Online publication date: Jan-2017
    • (2017)Virtual Two-Port Memory Architecture for Asymmetric Memory Technologies2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)10.1109/VLSID.2017.13(47-52)Online publication date: Jan-2017
    • (2016)WOM-Code Solutions for Low Latency and High Endurance in Phase Change MemoryIEEE Transactions on Computers10.1109/TC.2015.250655565:4(1025-1040)Online publication date: 1-Apr-2016
    • (2016)CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2016.7446056(90-101)Online publication date: Mar-2016
    • (2015)Adaptive Burst-Writes (ABW)ACM Transactions on Design Automation of Electronic Systems10.1145/275375721:1(1-26)Online publication date: 2-Dec-2015
    • Show More Cited By

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