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- research-articleJune 2012
Write performance improvement by hiding R drift latency in phase-change RAM
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 897–906https://doi.org/10.1145/2228360.2228520Phase-change RAM (PRAM) is considered to be one of the most promising candidates to complement or replace DRAM in the near future. However, it is imperative to overcome the limitations of PRAM, especially, long write latency for its widespread ...
- research-articleJune 2012
Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 888–896https://doi.org/10.1145/2228360.2228519Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this ...
- research-articleJune 2011
Power management of hybrid DRAM/PRAM-based main memory
DAC '11: Proceedings of the 48th Design Automation ConferencePages 59–64https://doi.org/10.1145/2024724.2024738Hybrid main memory consisting of DRAM and non-volatile memory is attractive since the non-volatile memory can give the advantage of low standby power while DRAM provides high performance and better active power. In this work, we address the power ...
- research-articleDecember 2010
Design exploration of hybrid caches with disparate memory technologies
ACM Transactions on Architecture and Code Optimization (TACO), Volume 7, Issue 3Article No.: 15, Pages 1–34https://doi.org/10.1145/1880037.1880040Traditional multilevel SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, core--to--cache balance, power consumption, and design complexity. New advancements in ...