research-article

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs

Authors:

Chia-Chun TsaiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 3

Article No.: 34, Pages 1 - 22

https://doi.org/10.1145/2209291.2209307

Published: 05 July 2012 Publication History

Abstract

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, Multiple Dynamic Supply Voltage (MDSV) designs are proposed as an efficient solution for power savings. However, the increasing variability of clock skew during the switching of power modes leads to an increase in the complication of clock skew reduction in MDSV designs. In this article, we propose a load-balanced clock tree synthesizer with Adjustable Delay Buffer (ADB) insertion for clock skew reduction in MDSV designs. The clock tree synthesizer adopts the Minimum Spanning Tree (MST) metric to estimate the interconnect capacitance and execute the graph-theoretic clustering. The power-mode-guided optimization is also embedded into the clock tree synthesizer for improving additional area overhead in the step of ADB insertion. After constructing the initial buffered clock tree, we insert the ADBs with delay value assignments to reduce clock skew in MDSV designs. The ADBs can be used to produce additional delays, hence the clock latencies and skew become tunable in a clock tree. An efficient algorithm of ADB insertion for the minimization of clock skew, area, and runtime in MDSV designs has been presented. Comparing with the state-of-the-art algorithm of ADB insertion, experimental results show maximum 42.40% area overhead improvement. With the power-mode-guided optimization, the maximum improvement of area overhead can increase to 47.87%.

References

[1]

Chao, T.-H., Hsu, Y.-C., Ho, J.-M., and B., K. A. 1992. Zero skew clock routing with minimum wirelength. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 39, 11, 799--814.

[2]

Chen, Y. P. and Wong, D. F. 1996. An algorithm for zero-skew clock tree routing with buffer insertion (edtc'96). In Proceedings of the European Design and Test Conference. IEEE Computer Society, Los Alamitos, CA, 230--236.

Digital Library

[3]

Edahiro, M. 1993. A clustering-based optimization algorithm in zero-skew routings. In Proceedings of the ACM/IEEE Design Automation Conference (DAC'93). ACM, New York, 612--616.

Digital Library

[4]

Edahiro, M. 1994. An efficient zero-skew routing algorithm. In Proceedings of the ACM/IEEE Design Automation Conference (DAC'94). ACM, New York, 375--380.

Digital Library

[5]

Hu, S. and Hu, J. 2007. Unified adaptivity optimization of clock and logic signals. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'07). IEEE Computer Society, Los Alamitos, CA, 125--130.

Digital Library

[6]

Jain, A. K., Murty, M. N., and Flynn, P. J. 1999. Data clustering: a review. ACM Comput. Surv. 31, 3, 264--323.

Digital Library

[7]

Johnston, T. K. 1999. Clock tree adjustable buffer. U. S. Patent 7571406B2.

[8]

Khandelwal, V. and Srivastava, A. 2007. Variability-Driven formulation for simultaneous gate sizing and post-silicon tunability allocation. In Proceedings of the International Symposium on Physical Design (ISPD'07). ACM, New York, 11--18.

Digital Library

[9]

Kurd, N. A., Barkarullah, J. S., Dizon, R. O., Fletcher, T. D., and Madland, P. D. 2001. A multigigahertz clocking scheme for the pentium 4 microprocessor. IEEE J. Solid-State Circ. 36, 11, 1647--1653.

[10]

Liu, I.-M., Chou, T.-L.,Wong, D. F., and Aziz, A. 2000. Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. In Proceedings of the International Symposium on Physical Design (ISPD'00). ACM, New York, 33--38.

Digital Library

[11]

Lung, C.-L., Zeng, Z.-Y., Chou, C.-H., and Chang, S.-C. 2010. Clock skew optimization considering complicated power modes. In Proceedings of the Conference on Design, Automation, and Test in Europe (DATE'10). 1474--1480.

Digital Library

[12]

Mehta, A. D., Chen, Y.-P., Menezes, N., Wong, D. F., and Pileggi, L. T. 1997. Clustering and load balancing for buffered clock tree synthesis. In Proceedings IEEE International Conference on Computer Design (ICCD'97). IEEE Computer Society, Los Alamitos, CA, USA, 217--223.

Digital Library

[13]

R.-S., Tsay. 1993. An exact zero-skew clock routing algorithm. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 12, 2, 242--249.

Digital Library

[14]

Roberts, G. N. 1994. Adjustable buffer driver. U. S. Patent 5361003.

[15]

Shelar, R. S. 2007. An efficient clustering algorithm for low power clock tree synthesis. In Proceedings of the International Symposium on Physical Design (ISPD'07). ACM, New York, 181--188.

Digital Library

[16]

Su, Y.-S., Hon, W.-K., Yang, C.-C., Chang, S.-C., and Chang, Y.-J. 2010. Clock skew minimization in multi-voltage mode designs using adjustable delay buffers. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 29, 12, 1921--1930.

Digital Library

[17]

Takahashi, E., Kasai, Y., Murakawa, M., and Higuchi, T. 2003. A post-silicon clock timing adjustment using genetic algorithms. In Digest of Technical Papers of the Symposium on VLSI Circuits. 13--16.

[18]

Tam, S., Limaye, R. D., and Desai, U. N. 2003. Clock generation and distribution for the 130-nm itaniumr 2 processor with 6-mb on-die l3 cache. IEEE J. Solid-State Circ. 39, 4, 636--642.

[19]

Tam, S., Rusu, S., Desai, U. N., Kim, R., Zhang, J., and Young, I. 2000. Clock generation and distribution for the first ia-64 microprocessor. IEEE J. Solid-State Circ. 35, 11, 1545--1552.

[20]

Tsai, J.-L., Chen, T.-H., and C. C.-P., C. 2004. Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 23, 4, 565--572.

Digital Library

[21]

Tsai, J.-L., Zhang, L., and Che, C. C.-P. 2005. Statistical timing analysis driven post-silicon-tunable clock-tree synthesis. In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD'05). IEEE Computer Society, Los Alamitos, CA, 575--581.

Digital Library

Cited By

Chentouf MStevmelin FAlaoui Ismaili Z(2021)Power-aware hold optimization for ASIC physical synthesisIntegration10.1016/j.vlsi.2020.08.00376(13-24)Online publication date: Jan-2021
https://doi.org/10.1016/j.vlsi.2020.08.003
Huang SCheng C(2016)Power-mode-aware buffer synthesis for low-power clock skew minimizationIEICE Electronics Express10.1587/elex.13.2016051113:14(20160511-20160511)Online publication date: 2016
https://doi.org/10.1587/elex.13.20160511
Tsai C(2016)2.5D X-Clock Tree Construction Based on Stacked-Layer Combination of Multivoltage Islands2016 International Symposium on Computer, Consumer and Control (IS3C)10.1109/IS3C.2016.118(443-446)Online publication date: Jul-2016
https://doi.org/10.1109/IS3C.2016.118
Show More Cited By

Index Terms

Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

Recommendations

Low-Power Clock Tree Synthesis for 3D-ICs

We propose efficient algorithms to construct a low-power clock tree for through-silicon-via (TSV)-based 3D-ICs. We use shutdown gates to save clock trees’ dynamic power, which selectively turn off certain clock tree branches to avoid unnecessary clock ...
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

It is well known that clock skew minimization becomes critical in high-performance VLSI designs. In this paper, the assignment of adjustable delay buffers(ADBs) is applied to minimize the clock skew in a buffered clock tree in a multi-voltage mode ...
An efficient algorithm of adjustable delay buffer insertion for clock skew minimization in multiple dynamic supply voltage designs
ASPDAC '11: Proceedings of the 16th Asia and South Pacific Design Automation Conference

Power consumption is known to be a crucial issue in current IC designs. To tackle this problem, multiple dynamic supply voltage (MDSV) designs are proposed as an efficient solution in modern IC designs. However, the increasing variability of clock skew ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 17, Issue 3

Special section on verification challenges in the concurrent world

June 2012

377 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2209291

Issue’s Table of Contents

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 July 2012

Accepted: 01 February 2012

Revised: 01 December 2011

Received: 01 April 2011

Published in TODAES Volume 17, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
299
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)0

Reflects downloads up to 29 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chentouf MStevmelin FAlaoui Ismaili Z(2021)Power-aware hold optimization for ASIC physical synthesisIntegration10.1016/j.vlsi.2020.08.00376(13-24)Online publication date: Jan-2021
https://doi.org/10.1016/j.vlsi.2020.08.003
Huang SCheng C(2016)Power-mode-aware buffer synthesis for low-power clock skew minimizationIEICE Electronics Express10.1587/elex.13.2016051113:14(20160511-20160511)Online publication date: 2016
https://doi.org/10.1587/elex.13.20160511
Tsai C(2016)2.5D X-Clock Tree Construction Based on Stacked-Layer Combination of Multivoltage Islands2016 International Symposium on Computer, Consumer and Control (IS3C)10.1109/IS3C.2016.118(443-446)Online publication date: Jul-2016
https://doi.org/10.1109/IS3C.2016.118
Llanos RSousa DTerres MBontorin GReis RJohann M(2015)Energy-efficient Level Shifter topology2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2015.7347600(148-151)Online publication date: Sep-2015
https://doi.org/10.1109/PATMOS.2015.7347600
Lin HChuang YYang ZHo T(2014)Pulsed-Latch Utilization for Clock-Tree Power OptimizationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2013.225221122:4(721-733)Online publication date: 1-Apr-2014
https://dl.acm.org/doi/10.1109/TVLSI.2013.2252211
Terres MMeinhardt CBontorin GReis R(2014)Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs2014 IEEE 5th Latin American Symposium on Circuits and Systems10.1109/LASCAS.2014.6820313(1-4)Online publication date: Feb-2014
https://doi.org/10.1109/LASCAS.2014.6820313
Yan JChen ZAyala JJones AMadden PCoskun A(2013)Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designsProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483093(203-208)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483093
Lin MChang YHung C(undefined)Recent research development and new challenges in analog layout synthesis2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2016.7428080(617-622)
https://dl.acm.org/doi/10.1109/ASPDAC.2016.7428080

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents