Article

Layer minimization of escape routing in area array packaging

Authors:

Renshen Wang,

Rui Shi,

Chung-Kuan ChengAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 815 - 819

https://doi.org/10.1145/1233501.1233668

Published: 05 November 2006 Publication History

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Abstract

We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. The triangular patterns are generated in a reverse order from the last to the first layer. We demonstrate that the triangular pin sequence maximizes the sum of escape pins in the accumulated layers and thus minimize the number of escape routing layers. A test case is presented to illustrate the approach.

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E. Winkler, "Escape Routing from Chip Scale Packages," IEEE/CPMT Int. Electronics Manufacturing Technology Symp., pp. 393--401, 1996.

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M. Horiuchi, E. Yoda, Y. Takeuchi, "Escape Routing Design to Reduce the Number of Layers in Area Array Packaging," IEEE Trans. on Advanced Packaging, vol.23, no.4, pp. 686--691, Nov. 2000.

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R. Shi, H. Chen, C.-K. Cheng, D. Beckman, D. Huang, "Layer Count Reduction for Area Array Escape Routing," Int. Conf. & Exhibition on Device Packaging, Scottsdale, 2005

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Cited By

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Yin SJin MChen GGong GMao WLu H(2023)Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB RoutingIEEE Access10.1109/ACCESS.2023.332358911(113712-113725)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3323589
Ahmadinejad AZarrabi-Zadeh H(2017)Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258576136:3(412-420)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2585761
Nguyen THill CHollenberg LJames M(2017)Fan-out Estimation in Spin-based Quantum Computer Scale-upScientific Reports10.1038/s41598-017-13308-07:1Online publication date: 17-Oct-2017
https://doi.org/10.1038/s41598-017-13308-0
Show More Cited By

Index Terms

Layer minimization of escape routing in area array packaging
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
  2. Hardware validation
2. Theory of computation
  1. Design and analysis of algorithms
    1. Approximation algorithms analysis
      1. Routing and network design problems

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Information & Contributors

Information

Published In

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06

Sponsor:

SIGDA
IEEE-CAS
IEEE-CS

ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

View all

Yin SJin MChen GGong GMao WLu H(2023)Unet-Astar: A Deep Learning-Based Fast Routing Algorithm for Unified PCB RoutingIEEE Access10.1109/ACCESS.2023.332358911(113712-113725)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3323589
Ahmadinejad AZarrabi-Zadeh H(2017)Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.258576136:3(412-420)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2585761
Nguyen THill CHollenberg LJames M(2017)Fan-out Estimation in Spin-based Quantum Computer Scale-upScientific Reports10.1038/s41598-017-13308-07:1Online publication date: 17-Oct-2017
https://doi.org/10.1038/s41598-017-13308-0
Ho YLee HLee WChang YChang CLin IShen C(2014)Obstacle-Avoiding Free-Assignment Routing for Flip-Chip DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228527533:2(224-236)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1109/TCAD.2013.2285275
Yan JTseng YYen C(2014)Feasible region assignment of routing nets in single-layer routing2014 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2014.6865148(393-396)Online publication date: Jun-2014
https://doi.org/10.1109/ISCAS.2014.6865148
Wang KWang HDong SKoh CSze C(2013)Escape routing of mixed-pattern signals based on staggered-pin-array PCBsProceedings of the 2013 ACM International symposium on Physical Design10.1145/2451916.2451941(93-100)Online publication date: 24-Mar-2013
https://dl.acm.org/doi/10.1145/2451916.2451941
Ho YLee HChang Y(2013)Escape Routing for Staggered-Pin-Array PCBsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.225953932:9(1347-1356)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1109/TCAD.2013.2259539
Yuan-Kai Ho Xin-Wei Shih Yao-Wen Chang Chung-Kuan Cheng (2013)Layer minimization in escape routing for staggered-pin-array PCBs2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASPDAC.2013.6509594(187-192)Online publication date: Jan-2013
https://doi.org/10.1109/ASPDAC.2013.6509594
Lee PLee HHo YChang YChang CLin IShen CGroeneveld PSciuto DHassoun S(2012)Obstacle-avoiding free-assignment routing for flip-chip designsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228558(1088-1093)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228558
Yan TWong M(2012)Correctly Model the Diagonal Capacity in Escape RoutingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.216925831:2(285-293)Online publication date: 1-Feb-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2169258
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Escape routing of mixed-pattern signals based on staggered-pin-array PCBs

New optimal layer assignment for bus-oriented escape routing

Ordered escape routing via routability-driven pin assignment