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A bounded 2D contour searching algorithm for floorplan design with arbitrarily shaped rectilinear and soft modules

Published: 01 July 1993 Publication History
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References

[1]
Lu She, A Macro Cell Placement Algorithm Using Mathematical Programming Techniques, Ph.D dissertation, Stanford University, March 1989.
[2]
D.F. Wong and C.L. Liu, "An Optimal Algorithm for Floorplan Area Optimization", in Proc. 27th A CM/IEEE Design Automation Conf., (1990), pp.180-186.
[3]
H. Onodera, Y. Taniguchi, and K. Tamaru, "Branch-and-Bound Placement for Building Block Layout", presented at, 1990 international Workshop on Layout Synthesis, 1990. "
[4]
Albert H. Chao, Eric M. Nequist, Thanh D. Vuong, "Direct Solution of Performance Constraints During Placement", in IEEE 1990 Custom Integrated Circuits Conference, pp.27.2.1-27.2.4.
[5]
S. Kirkpatrick, C. Gelatt, and M. Vecchi, "Optimization by Simulated Annealing", Science, voi.220, n.4598, May 13, 1983, pp.671.
[6]
Carl Sechen, Placement and Global Routing of Integrated Circuits Using Simulated Annealing, Ph.D dissertation, Univ. of California, Berkeley, 1987.
[7]
HyunchulShin, Alberto L. Sangiovanni-Vincentelli, and Carlo tI. S@quin, "Two-Dimensional Compaction by Zone Refining" 23rd Design Automation Conference, 1986, pp.i15-122.
[8]
W.H. Wolf, R.G. Mathews, :I.A. Mewkirk, and R.W. Dutton, "Algorithms for Optimizing Two-Dimensional Symbolic Layout Compaction", IEEE Trans. CAD of IC and Systems, CAD-7(4), 1988, pp.451-466.
[9]
Ping-San Tzeng and Carlo H. S@quin, "Macroblock Placement Using Efficient 2-D Compaction", in Advanced Research in VLSI: Proceedings of the 1991 University of California/Santa Cruz Conference, edited by Carlo H. S@quin, MIT Press, 1991, pp.178-191.
[10]
W.W.-M. Dai and E.S. Kuh, "Simultaneous Floorplanning and Global Routing for Hierarchical Building Block Layout", IEEE Trans on Computer.Aided Design of Integrated Circuits and Systems, CAD-6(5),1987, pp.828-837.
[11]
G. Vijayan and R.S. Tsay, "Floorplanning by Topological Constraint Reduction" 1990 IEEE International Conference on Computer-Aided Design, pp.106-109.
[12]
Tsu-chang Lee, "Multiple-Layer Contour Searching Method and Apparatus for Circuit Building Block Placement", US patent pending.

Cited By

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  • (2010)VLSI layout algorithmsAlgorithms and theory of computation handbook10.5555/1882723.1882731(8-8)Online publication date: 1-Jan-2010
  • (2006)Nonrectangular shaping and sizing of soft modules for floorplan-design improvementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81989623:1(71-79)Online publication date: 1-Nov-2006
  • (2006)On extending slicing floorplan to handle L/T-shaped modules and abutment constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.92483320:6(800-807)Online publication date: 1-Nov-2006
  • Show More Cited By

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cover image ACM Conferences
DAC '93: Proceedings of the 30th international Design Automation Conference
July 1993
768 pages
ISBN:0897915771
DOI:10.1145/157485
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 July 1993

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June 14 - 18, 1993
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Cited By

View all
  • (2010)VLSI layout algorithmsAlgorithms and theory of computation handbook10.5555/1882723.1882731(8-8)Online publication date: 1-Jan-2010
  • (2006)Nonrectangular shaping and sizing of soft modules for floorplan-design improvementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2003.81989623:1(71-79)Online publication date: 1-Nov-2006
  • (2006)On extending slicing floorplan to handle L/T-shaped modules and abutment constraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.92483320:6(800-807)Online publication date: 1-Nov-2006
  • (2006)Sequence-pair approach for rectilinear module placementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.75293118:4(484-493)Online publication date: 1-Nov-2006
  • (2006)Module packing based on the BSG-structure and IC layout applicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.70383217:6(519-530)Online publication date: 1-Nov-2006
  • (2003)Rectilinear block placement using B*-treesACM Transactions on Design Automation of Electronic Systems10.1145/762488.7624908:2(188-202)Online publication date: 1-Apr-2003
  • (2002)Arbitrary Convex and Concave Rectilinear Module Packing Using TCGProceedings of the conference on Design, automation and test in Europe10.5555/882452.874389Online publication date: 4-Mar-2002
  • (2002)Arbitrarily shaped rectilinear module placement using the transitive closure graph representationIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.80843110:6(886-901)Online publication date: 1-Dec-2002
  • (2002)Arbitrary convex and concave rectilinear module packing using TCGProceedings 2002 Design, Automation and Test in Europe Conference and Exhibition10.1109/DATE.2002.998251(69-75)Online publication date: 2002
  • (2001)Constrained polygon transformations for incremental floorplanningACM Transactions on Design Automation of Electronic Systems10.1145/383251.3832556:3(322-342)Online publication date: 1-Jul-2001
  • Show More Cited By

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