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An algorithm for diagnosing two-line bridging faults in combinational circuits

Authors:

Sreejit Chakravarty,

Yiming GongAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 520 - 524

https://doi.org/10.1145/157485.165012

Published: 01 July 1993 Publication History

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References

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S. Chakravarty, M. Liu, "IDDQ Measurement Based Diagnosis of Bridging Faults", Journal of Electronic Testing: Theory and Application ( Special Issue on IDDQ Testing ). Kluwer Academic Publishers.

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S. Chakravarty, Y. Gong, "An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits", Tech. Rep. No. 92-26, Dept. of Comp. Science, SUNY at Buffalo, Buffalo, NY 14260.

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F.T.Ferguson and J.P.Shen, "A CMOS Fault Extractor for Inductive Fault Analysis", IEEE Trans. on Comput.-Aided Design, Vol. 7, No. 11, pp. 1181-1194.

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Cited By

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Nandakumar BChillarige SL’Esperance NZimmerman JRedburn R(2023)Addressing Physically Aware Diagnosis Challenges in Hierarchical Core Based Designs2023 IEEE International Test Conference India (ITC India)10.1109/ITCIndia59034.2023.10235457(1-8)Online publication date: 23-Jul-2023
https://doi.org/10.1109/ITCIndia59034.2023.10235457
Nandakumar BMaheshwari MChillarige SRedburn RZimmerman JEsperance NDziarcak E(2022)Scaling physically aware logic diagnosis to complex high volume 7nm server processors2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00042(340-347)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00042
Tsai WLiu WLi J(2012)Structural Reduction Techniques for Logic-Chain Bridging Fault DiagnosisIEEE Transactions on Computers10.1109/TC.2011.9861:7(928-938)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1109/TC.2011.98
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Index Terms

An algorithm for diagnosing two-line bridging faults in combinational circuits
1. Hardware
  1. Hardware test
    1. Test-pattern generation and fault simulation
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory
      1. Paths and connectivity problems

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Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 July 1993

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DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Nandakumar BChillarige SL’Esperance NZimmerman JRedburn R(2023)Addressing Physically Aware Diagnosis Challenges in Hierarchical Core Based Designs2023 IEEE International Test Conference India (ITC India)10.1109/ITCIndia59034.2023.10235457(1-8)Online publication date: 23-Jul-2023
https://doi.org/10.1109/ITCIndia59034.2023.10235457
Nandakumar BMaheshwari MChillarige SRedburn RZimmerman JEsperance NDziarcak E(2022)Scaling physically aware logic diagnosis to complex high volume 7nm server processors2022 IEEE International Test Conference (ITC)10.1109/ITC50671.2022.00042(340-347)Online publication date: Sep-2022
https://doi.org/10.1109/ITC50671.2022.00042
Tsai WLiu WLi J(2012)Structural Reduction Techniques for Logic-Chain Bridging Fault DiagnosisIEEE Transactions on Computers10.1109/TC.2011.9861:7(928-938)Online publication date: 1-Jul-2012
https://dl.acm.org/doi/10.1109/TC.2011.98
Jagan LKamakoti V(2010)Test and Diagnostic Trends for Nanometer TechnologyIETE Technical Review10.4103/0256-4602.7258027:6(430)Online publication date: 2010
https://doi.org/10.4103/0256-4602.72580
Pomeranz IReddy S(2010)Selection of a fault model for fault diagnosis based on unique responsesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.202550318:11(1533-1543)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2025503
Pomeranz IReddy S(2010)Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault PairsProceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems10.1109/DFT.2010.49(349-357)Online publication date: 6-Oct-2010
https://dl.acm.org/doi/10.1109/DFT.2010.49
Pomeranz IReddy SBenini LDe Micheli GAl-Hashimi BMueller W(2009)Selection of a fault model for fault diagnosis based on unique responsesProceedings of the Conference on Design, Automation and Test in Europe10.5555/1874620.1874862(994-999)Online publication date: 20-Apr-2009
https://dl.acm.org/doi/10.5555/1874620.1874862
Benabboud YBosio ADilillo LGirard PPravossoudovitch SVirazel ABouzaida LIzaute I(2009)Comprehensive bridging fault diagnosis based on the SLAT paradigmProceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems10.1109/DDECS.2009.5012142(264-269)Online publication date: 15-Apr-2009
https://dl.acm.org/doi/10.1109/DDECS.2009.5012142
Pomeranz IReddy S(2009)Selection of a fault model for fault diagnosis based on unique responses2009 Design, Automation & Test in Europe Conference & Exhibition10.1109/DATE.2009.5090809(994-999)Online publication date: Apr-2009
https://doi.org/10.1109/DATE.2009.5090809
Chen PLi JChao H(2009)Bridging Fault Diagnosis to Identify the Layer of Systematic DefectsProceedings of the 2009 Asian Test Symposium10.1109/ATS.2009.58(349-354)Online publication date: 23-Nov-2009
https://dl.acm.org/doi/10.1109/ATS.2009.58
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