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Coordinated resource optimization in behavioral synthesis

Published: 08 March 2010 Publication History

Abstract

Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapath in a typical design is composed of different kinds of components, including functional units, registers and multiplexers. To optimize the overall resource usage, a behavioral synthesis tool should consider all kinds of components at the same time. However, most previous work on behavioral synthesis has the limitations of (i) not being able to consider all kinds of resources globally, and/or (ii) separating the synthesis process into a sequence of optimization steps without a consistent optimization objective. In this paper we present a behavioral synthesis flow in which all types of components in the datapath are modeled and optimized consistently. The key idea is to feed to the scheduler the intentions for sharing functional units and registers in favor of the global optimization goal (such as total area), so that the scheduler could generate a schedule that makes the sharing intentions feasible. Experiments show that compared to the solution of minimizing functional unit requirements in scheduling and using the least number of functional units and registers in binding, our solution achieves a 24% reduction in total area; compared to the online tool provided by c-to-verilog.com, our solution achieves a 30% reduction on average.

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http://www.c-to-verilog.com.

Cited By

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  • (2013)Improving polyhedral code generation for high-level synthesisProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555707(1-10)Online publication date: 29-Sep-2013
  • (2013)FPGA latency optimization using system-level transformations and DFG restructuringProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485658(1553-1558)Online publication date: 18-Mar-2013
  • (2013)Share with careProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485657(1547-1552)Online publication date: 18-Mar-2013
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Information & Contributors

Information

Published In

cover image ACM Conferences
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
March 2010
1868 pages
ISBN:9783981080162

Sponsors

  • EDAA: European Design Automation Association
  • ECSI
  • EDAC: Electronic Design Automation Consortium
  • SIGDA: ACM Special Interest Group on Design Automation
  • The IEEE Computer Society TTTC
  • The IEEE Computer Society DATC
  • The Russian Academy of Sciences: The Russian Academy of Sciences

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

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DATE '10
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE '10: Design, Automation and Test in Europe
March 8 - 12, 2010
Germany, Dresden

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2013)Improving polyhedral code generation for high-level synthesisProceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis10.5555/2555692.2555707(1-10)Online publication date: 29-Sep-2013
  • (2013)FPGA latency optimization using system-level transformations and DFG restructuringProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485658(1553-1558)Online publication date: 18-Mar-2013
  • (2013)Share with careProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485657(1547-1552)Online publication date: 18-Mar-2013
  • (2012)Towards layout-friendly high-level synthesisProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160952(165-172)Online publication date: 25-Mar-2012

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