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Low-energy embedded FPGA structures

Authors:

Eric Kusse,

Jan RabaeyAuthors Info & Claims

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

Pages 155 - 160

https://doi.org/10.1145/280756.280873

Published: 10 August 1998 Publication History

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Abstract

This paper introduces an energy-efficient FPGA module, intended for embedded implementations. The main features of the proposed cell include a rich local-interconnect network, which drastically reduces the energy dissipated in the wiring, and a dual-voltage scheme that allows pass-transistor networks to operate at low-voltages yet maintain decent performance. Simulations on a benchmark set demonstrate that the proposed module succeeds in its goal of reducing energy consumption by an order of magnitude over existing implementations.

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Baidya PMandal SPaul R(2024)Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable ArchitectureIEEE Access10.1109/ACCESS.2024.340123512(68814-68827)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3401235
Umapathy KMuthukumaran DChandramohan SSivakumar MJames O(2023)Low Power Methodologies for FPGA—An OverviewLow Power Architectures for IoT Applications10.1007/978-981-99-0639-0_4(85-97)Online publication date: 5-Apr-2023
https://doi.org/10.1007/978-981-99-0639-0_4
Banik SBogdanov ARegazzoni F(2015)Exploring the energy consumption of lightweight blockciphers in FPGA2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393308(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/ReConFig.2015.7393308
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Information

Published In

ISLPED '98: Proceedings of the 1998 international symposium on Low power electronics and design

August 1998

318 pages

ISBN:1581130597

DOI:10.1145/280756

Chairmen:
Anantha Chandrakasan
MIT
,
Sayfe Kiaei
Motorola

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 August 1998

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ISLPED98

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IEEE-EDS
SIGDA
IEEE-SSCS
IEEE-CAS

ISLPED98: International Symposium on Low Power Electronics and Design

August 10 - 12, 1998

California, Monterey, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Baidya PMandal SPaul R(2024)Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable ArchitectureIEEE Access10.1109/ACCESS.2024.340123512(68814-68827)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3401235
Umapathy KMuthukumaran DChandramohan SSivakumar MJames O(2023)Low Power Methodologies for FPGA—An OverviewLow Power Architectures for IoT Applications10.1007/978-981-99-0639-0_4(85-97)Online publication date: 5-Apr-2023
https://doi.org/10.1007/978-981-99-0639-0_4
Banik SBogdanov ARegazzoni F(2015)Exploring the energy consumption of lightweight blockciphers in FPGA2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig.2015.7393308(1-6)Online publication date: Dec-2015
https://doi.org/10.1109/ReConFig.2015.7393308
Roux Rvan Schoor Gvan Vuuren P(2014)A survey on reducing reconfiguration cost: reconfigurable PID control as a special caseIFAC Proceedings Volumes10.3182/20140824-6-ZA-1003.0154447:3(1320-1330)Online publication date: 2014
https://doi.org/10.3182/20140824-6-ZA-1003.01544
Hou JYu HHa YLiu X(2013)The architecture and placement algorithm for a uni-directional routing based 3D FPGA2013 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2013.6718325(28-33)Online publication date: Dec-2013
https://doi.org/10.1109/FPT.2013.6718325
Velegalati RShah KKaps J(2013)Glitch Detection in Hardware Implementations on FPGAs Using Delay Based Sampling TechniquesProceedings of the 2013 Euromicro Conference on Digital System Design10.1109/DSD.2013.107(947-954)Online publication date: 4-Sep-2013
https://dl.acm.org/doi/10.1109/DSD.2013.107
HUANG JCHEN CHSU WLIN YJOU J(2012)Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island DelayIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E95.A.559E95-A:2(559-566)Online publication date: 2012
https://doi.org/10.1587/transfun.E95.A.559
Shrivastava ALach JCalhoun BShanbhag NPoncino MChou PAmerasekera A(2012)A charge pump based receiver circuit for voltage scaled interconnectProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333733(327-332)Online publication date: 30-Jul-2012
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Muthusamy SSubramaniam V(2012)Low-power dissipation using FPGA architecture2012 International Conference on Devices, Circuits and Systems (ICDCS)10.1109/ICDCSyst.2012.6188752(418-421)Online publication date: Mar-2012
https://doi.org/10.1109/ICDCSyst.2012.6188752
le Roux Rvan Schoor Gvan Vuuren P(2012)Block RAM Implementation of a Reconfigurable Real-time PID ControllerProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.203(1383-1390)Online publication date: 25-Jun-2012
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