Nothing Special   »   [go: up one dir, main page]

skip to main content
10.1145/1284480.1284527acmconferencesArticle/Chapter ViewAbstractPublication PagessbcciConference Proceedingsconference-collections
Article

RoSA: a reconfigurable stream-based architecture

Published: 03 September 2007 Publication History

Abstract

The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques and hardware reuse to accelerate the execution of stream-based applications. The results showed that RoSA achieved performance gains of more than 74% over the code that can be executed concurrently and 55% of the total cost of the applications.

References

[1]
Agostini, L.; Silva, I.; Bampi, S. Pipelined Fast 2-D DCT Architecture for JPEG Image Compression. In Proceedings of 14th Symposium on Integrated Circuits and System Design (SBCCI .01) (GO, Brazil, Sept. 10--15, 2001). IEEE Computer Society Press, Washington, DC, USA, 2001, 226--231.
[2]
Alippi, C. et al. A DAG-Based Design Approach for Reconfigurable VLIW Processors. In Design, Automation and Test in Europe Conference and Exhibition (DATE .99) (Munich, Germany, Mar. 09--12, 1999), IEEE Computer Society Press, Washington, DC, USA, 1999, 778--780.
[3]
Azevedo, A. et al. Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. In The 16th IEEE International Workshop on Rapid System Prototyping (RSP .05) (Montreal, CA, Jun. 8--10, 2005), IEEE Computer Society Press, Washington, DC, USA, 2005, 255--257.
[4]
Goldstein, S. C. et al. PipeRench: A Coprocessor for Streaming Multimedia Acceleration In Proceedings of The 26th Annual International Symposium on Computer Architecture (ISCA .99) (Atlanta, Georgia, USA, May 02--04, 1999), IEEE Computer Society Press, Washington, DC, USA, 1999, 28--39.
[5]
Guccione, S. A. and Gonzalez, M. J. FFT on reconfigurable hardware. In Proceedings of The International Society for Optical Engineering (Orlando, FL, USA, April 17--18 1995), Society of Photo-Optical Instrumentation Engineers, USA, 1995, 30--41.
[6]
Hartenstein, R. Coarse Grain Reconfigurable Architectures. In Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC .01) (Yokohama, Japan, 30 Jan.-2 Feb., 2001), IEEE Computer Society Press, Washington, DC, USA, 2001, 564--569.
[7]
Herz, M. Memory Addressing Organization for Stream-based Reconfigurable Computing. In Proceedings of the 9th International Conference on Electronics, Circuits and Systems (ICECS .02) (Dubrovnik, Croatia, Sept. 15--18, 2002), IEEE Computer Society Press, Washington, DC, USA, 2002, Volume 2, 813--817.
[8]
Mangione-Smith, W. H. et al. Seeking Solutions in Configurable Computing. IEEE Computer, 30, 12 (Dec. 1997), 38--43.
[9]
Owens, J. D. et al. Media Processing Applications on the Imagine Stream Processor. In Proceedings of the 20th International Conference on Computer Design (ICCD'02) (Freiburg, Germany, September 16--18, 2002), IEEE Computer Society Press, Washington, DC, USA, 2002, 295--302.
[10]
Platzner, M. Reconfigurable Computer Architectures. e&i Elektrotechnik und Informationstechnik, 115, 3, Springer, 1998, 143--148.
[11]
Pozzi, L. Compilation Techniques for Exploiting Instruction Level Parallelism, a Survey. Technical Report TR-99.2, Politecnico di Milano, Milan, Italy, 1999. http://icwww.epfl.ch/~lpozzi//pub.html
[12]
Pozzi, L. Methodologies for the Design of Application-Specific Reconfigurable VLIW Processors. Ph.D. Thesis, Politecnico di Milano, Milan, Italy, 2000.
[13]
Rau, B. R. and Fisher, J. A. Instruction-Level Parallel Processing: History, Overview and Perspective. Technical Report HPL-92-132, HP Laboratories, 1992. http://www.hpl.hp.com/
[14]
Singh, H. et al. MorphoSys: An Integrated Re-configurable Architecture. In Proceedings of the NATO RTO Symposium of System Concepts and Integration (Monterey, CA, USA, April 20--22, 1998), 1998.
[15]
Singh, H. et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications. IEEE Trans. on Computers, 49, 5(May 2000), 465--481.
[16]
Sterpone, L. and Violante, M. ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications. In IEEE Design and Diagnostics of Electronic Circuits and Systems (DDECS .06) (Prague, Czech Republic, April 18--21, 2006), IEEE Computer Society Press, Washington, DC, USA, 52--56.
[17]
Taylor, M. B. et al. The RAW Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs. In Micro IEEE, 22, 2 (Mar-Apr 2002), 25--35.
[18]
The SPARC Architecture Manual-Version 8, www.sparc.org, 2007.
[19]
Todman, T. J. et al. Reconfigurable Computing: architectures and design methods. In IEE Proceedings Computers and Digital Techniques, 152, 2 (Mar. 2005). IEEE Computer Society Press, Washington, DC, USA, 2005, 193--207.
[20]
Vissers, K. A. Parallel Processing Architectures for Reconfigurable Systems. In Design, Automation and Test in Europe Conference and Exhibition (DATE .03) (Munich, Germany, Mar. 03-07, 2003), IEEE Computer Society Press, Washington, DC, USA, 2003, 396--397.
[21]
Wallace, G. K. The JPEG still picture compression standard. In IEEE Trans. On Consumer Electronics, 38, 1 (Feb. 1992), IEEE Computer Society Press, Washington, DC, USA, 1992.
[22]
Ye, Z. A. et al. CHIMAERA: A High-Performance Architecture with a Tightly-Coupled Reconfigurable Functional Unit. In Proceedings of the 27th Annual International Symposium on Computer Architecture (ISCA .00) (Vancouver, British Columbia, Canada, 2000), IEEE Computer Society Press, Washington, DC, USA, 2000, 225--235.
[23]
Ye, Z. A., Shenoy, N. and Banerjee, P. A C Compiler for a Processor with a Reconfigurable Functional Unit In Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays (Monterrey, CA, USA, Feb. 10--11, 2000), ACM Press, New York, NY, 2000, 95--100.

Cited By

View all
  • (2014)A reconfigurable processor architecture combining multi-core and reconfigurable processing unitsTelecommunications Systems10.1007/s11235-013-9791-155:3(333-344)Online publication date: 1-Mar-2014
  • (2010)System-level modeling of a Reconfigurable System on Chip for wireless sensor networks applications2010 International Conference on Intelligent and Advanced Systems10.1109/ICIAS.2010.5716264(1-5)Online publication date: Jun-2010
  • (2009)BRICKProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601942(1-6)Online publication date: 31-Aug-2009
  • Show More Cited By

Recommendations

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Conferences
SBCCI '07: Proceedings of the 20th annual conference on Integrated circuits and systems design
September 2007
382 pages
ISBN:9781595938169
DOI:10.1145/1284480
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 September 2007

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. coarse-grained
  2. reconfigurable architecture
  3. stream-based

Qualifiers

  • Article

Conference

SBCCI07
Sponsor:
SBCCI07: 20th Symposium on Integrated Circuits and System Design
September 3 - 6, 2007
Copacabana, Rio de Janeiro

Acceptance Rates

Overall Acceptance Rate 133 of 347 submissions, 38%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 14 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2014)A reconfigurable processor architecture combining multi-core and reconfigurable processing unitsTelecommunications Systems10.1007/s11235-013-9791-155:3(333-344)Online publication date: 1-Mar-2014
  • (2010)System-level modeling of a Reconfigurable System on Chip for wireless sensor networks applications2010 International Conference on Intelligent and Advanced Systems10.1109/ICIAS.2010.5716264(1-5)Online publication date: Jun-2010
  • (2009)BRICKProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601942(1-6)Online publication date: 31-Aug-2009
  • (2009)Signal Processing Domain Application Mapping on the Brick Reconfigurable ArrayProceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs10.1109/ReConFig.2009.85(356-361)Online publication date: 9-Dec-2009
  • (2008)Using traditional loop unrolling to fit application on a new hybrid reconfigurable architectureProceedings of the 2008 ACM symposium on Applied computing10.1145/1363686.1364049(1552-1553)Online publication date: 16-Mar-2008

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media