In this paper, we describe a platform that aims to help developers on the construction of embedded AR applications. The infrastructure is based on Field Programmable Gate Array and enables the creation of hardware based AR systems, contributing to high ...

System-level specification can benefit from the feature-rich UML visual notations. However, it is necessary to integrate UML into current SoC design flows. Unlike previous approaches that relied on code generation or static analysis, this paper proposes ...

With the increased demand for programmability in embedded applications, the pressure for producing high performance software in a timely fashion has grown over the years. For this reason, declarative languages, as they provide more abstraction than ...

The growing complexity of embedded systems has claimed for more software solutions in order to reduce the time-to-market. However, while this software decrease the development time of the embedded system functionalities , it must at the same time help ...

Over the last years, DVS (Dynamic Voltage Scaling) hasbeen adopted as an effective technique for reducing energyconsumption in embedded systems. In the context of hard real-time embedded systems, several scheduling approaches have been developed to ...

We present a novel page table organization for real-time and memory-constrained embedded systems. Increasingly many high-end embedded processors offer virtual memory support in the form of hardware Memory Management Unit. To implement virtual memory ...

Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper ...

Regarding MPSoCs, dynamic task allocation and task migration are still open research areas and, for both of them, there is no clear memory organization winner. While bus-connected systems commonly use a shared memory paradigm, NoC-based ones easily ...

The present paper reports the design of a CMOS circuit capable of codifying the natural logarithm of an analog voltage in the relative phase of a train of pulses. The circuit is aimed to the implementation of a scale-independent pattern recognition ...

We present a design approach for adaptive multiprocessors on chip, in particular for FPGA devices. The approach consists of two steps in which the hardware infrastructure is first generated and then, the single processors, the peripherals as well as the ...

This work presents the development of a dynamically reconfigurable computing platform targeting Virtex-II devices under control of a host system based on the Nios II soft-core processor from Altera. The platform, called Aquarius, controls the system by ...

The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. ...