article

Compiler-directed application mapping for NoC based chip multiprocessors

Authors:

Guangyu Chen,

Feihui Li,

Mahmut KandemirAuthors Info & Claims

ACM SIGPLAN Notices, Volume 42, Issue 7

Pages 155 - 157

https://doi.org/10.1145/1273444.1254796

Published: 13 June 2007 Publication History

Get Access

Abstract

The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multi-processor architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, processor mapping, data mapping, and packet routing. Our experimental result clearly shows that the proposed framework reduces energy consumption of our applications significantly (27.41% on average over a pure performance oriented application mapping strategy) as a result of improved locality of data accesses.

References

[1]

J. M. Anderson. Automatic Computation and Data Decomposition for Multiprocessors. Ph.D. Thesis, Computer Science Department, Stanford University, March 1997.

Digital Library

Google Scholar

[2]

L. Benini and G. D. Micheli. Powering NoCs: energy-efficient and reliable interconnect design for SoCs. In Proc. ISSS, 2001.

Digital Library

Google Scholar

[3]

G. Chen, F. Li, and M. Kandemir. Compiler-directed channel allocation for saving power in on-chip networks. In Proc. POPL, Charleston, SC, Jan. 2006.

Digital Library

Google Scholar

[4]

W. J. Dally and B. Towles. Route packets, not wires: on-chip interconnection networks. In Proc. DAC, Las Vegas, NV, June 2001.

Digital Library

Google Scholar

[5]

Virtutech Simics: http://www.virtutech.com/

Google Scholar

[6]

H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik. Orion: A power-performance simulator for interconnection networks. In Proc. MICRO, Nov. 2002.

Digital Library

Google Scholar

Cited By

View all

Saleem SHussain FAmin WAhmed RZikria YIshmanov FYu H(2023)A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based PlatformsIEEE Access10.1109/ACCESS.2023.332923311(122694-122721)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3329233
Amin WHussain FAnjum SKhan SBaloch NNain ZKim S(2020)Performance Evaluation of Application Mapping Approaches for Network-on-Chip DesignsIEEE Access10.1109/ACCESS.2020.29826758(63607-63631)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2982675
Pranzo MMazumdar S(2019)An analytical model for thread-core mapping for tiled CMPsPerformance Evaluation10.1016/j.peva.2019.102003(102003)Online publication date: Jun-2019
https://doi.org/10.1016/j.peva.2019.102003
Show More Cited By

Index Terms

Compiler-directed application mapping for NoC based chip multiprocessors
1. Software and its engineering
  1. Software notations and tools
    1. General programming languages

Recommendations

Compiler-directed application mapping for NoC based chip multiprocessors
LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems

The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multi-processor architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling, ...
Application mapping for chip multiprocessors
DAC '08: Proceedings of the 45th annual Design Automation Conference

The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fashion. The proposed compiler approach has four major steps: task scheduling,...
Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms

Application mapping is an important part of network-on-chip (NoC) design, it tries to map the application onto a NoC-based platform. Because mapping an application onto the mesh architecture is NP-hard, there is no known algorithm for solving this ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

ACM SIGPLAN Notices Volume 42, Issue 7

Proceedings of the 2007 LCTES conference

July 2007

241 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/1273444

Issue’s Table of Contents

LCTES '07: Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
June 2007
258 pages
ISBN:9781595936325
DOI:10.1145/1254766
General Chair:
Santosh Pande
Georgia Institute of Technology, USA
,
Program Chair:
Zhiyuan Li
Purdue University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 13 June 2007

Published in SIGPLAN Volume 42, Issue 7

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

17
Total Citations
View Citations
469
Total Downloads

Downloads (Last 12 months)8
Downloads (Last 6 weeks)0

Reflects downloads up to 14 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Saleem SHussain FAmin WAhmed RZikria YIshmanov FYu H(2023)A Survey on Dynamic Application Mapping Approaches for Real-Time Network-on-Chip-Based PlatformsIEEE Access10.1109/ACCESS.2023.332923311(122694-122721)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3329233
Amin WHussain FAnjum SKhan SBaloch NNain ZKim S(2020)Performance Evaluation of Application Mapping Approaches for Network-on-Chip DesignsIEEE Access10.1109/ACCESS.2020.29826758(63607-63631)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.2982675
Pranzo MMazumdar S(2019)An analytical model for thread-core mapping for tiled CMPsPerformance Evaluation10.1016/j.peva.2019.102003(102003)Online publication date: Jun-2019
https://doi.org/10.1016/j.peva.2019.102003
Wang JZhang MQiu M(2018)A Diffusional Schedule for Traffic Reducing on Network-on-Chip2018 5th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud)/2018 4th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom)10.1109/CSCloud/EdgeCom.2018.00044(206-210)Online publication date: Jun-2018
https://doi.org/10.1109/CSCloud/EdgeCom.2018.00044
Reza A(2017)Online multi-application mapping in photonic Network-on-Chip with mesh topologyOptical Switching and Networking10.1016/j.osn.2017.04.00225(100-108)Online publication date: Jul-2017
https://doi.org/10.1016/j.osn.2017.04.002
Reza AMirzaee R(2017)Non-preemptive offline multi-job mapping for a photonic network on a chipNano Communication Networks10.1016/j.nancom.2016.09.00411(11-23)Online publication date: Mar-2017
https://doi.org/10.1016/j.nancom.2016.09.004
Marcon CWebber TSusin A(2017)Models of computation for NoC mapping: Timing and energy saving awarenessMicroelectronics Journal10.1016/j.mejo.2016.09.00560(129-143)Online publication date: Feb-2017
https://doi.org/10.1016/j.mejo.2016.09.005
Wang YZhang ZHuang LJi W(2015)Memory-Aware NoC Application Mapping Based on Adaptive Genetic AlgorithmAlgorithms and Architectures for Parallel Processing10.1007/978-3-319-27119-4_7(91-102)Online publication date: 16-Dec-2015
https://doi.org/10.1007/978-3-319-27119-4_7
Hollis SJackson C(2013)Implementation and Evaluation of Skip-LinksAdoption and Optimization of Embedded and Real-Time Communication Systems10.4018/978-1-4666-2776-5.ch010(181-203)Online publication date: 2013
https://doi.org/10.4018/978-1-4666-2776-5.ch010
Sahu PChattopadhyay S(2013)A survey on application mapping strategies for Network-on-Chip designJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2012.10.00459:1(60-76)Online publication date: 1-Jan-2013
https://dl.acm.org/doi/10.1016/j.sysarc.2012.10.004
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Compiler-directed application mapping for NoC based chip multiprocessors

Application mapping for chip multiprocessors

Application mapping onto mesh-based network-on-chip using constructive heuristic algorithms