Nothing Special   »   [go: up one dir, main page]

skip to main content
article

Multiple wire reconnections based on implication flow graph

Published: 01 October 2006 Publication History

Abstract

Global flow optimization (GFO) can perform multiple fanout/fanin wire reconnections at a time by modeling the problem of multiple wire reconnections with a flow graph, and then solving the problem using the maxflow-mincut algorithm on the flow graph. In this article, we propose an efficient multiple wire reconnection technique that modifies the framework of GFO, and as a result, can obtain better optimization quality. First, we observe that the flow graph in GFO cannot fully characterize wire reconnections, which causes the GFO to lose optimality in several obvious cases. In addition, we find that fanin reconnection can have more optimization power than fanout reconnection, but requires more sophisticated modeling. We reformulate the problem of fanout/fanin reconnections by a new graph, called the implication flow graph (IFG). We show that the problem of wire reconnections on the implication flow graph is NP-complete and also propose an efficient heuristic on the new graph. To demonstrate the effectiveness of our proposed method, we conduct an application which utilizes the flexibility of the wire reconnections explored in the logic domain to further minimize interconnects in the physical layout. Our experimental results are very exciting.

References

[1]
Abramovici, M. Breuer, M. A., and Friedman, A. D. 1990. Digital Systems Testing and Testable Design, Computer Science, New York.
[2]
Berman C. L. and Trevillyan, L. H. 1991. Global flow optimization in automatic logic design. IEEE Trans. Comput. Aided Des. 10, (May), 557--564.
[3]
Chang, S. C., Cheng, K. T., Woo, N. S., and Marek-Sadowska, M. 1997. Post layout logic restructuring using alternative wires. IEEE Trans. Computer Aided Des. 16, (June) 587--596.
[4]
Chang, S. C., Chuang, J. C., and Wu, Z. Z. 1999. Synthesis for multiple input wires replacement of a gate for wiring consideration. In Digest of the International Conference on Computer Aided Design. 115--118.
[5]
Chang, S. C., Marek-Sadowska, M., and Cheng, K. T. 1996. Perturb and simplify: Multi-level boolean network optimizer. IEEE Trans. Comput. Aided Des. 15, (Nov.), 1494--1504.
[6]
Cheng and K. T. and Entrena, L. A. 1993. Multi-level logic optimization by redundancy addition and removal. In Proceedings of the European Conference on Design Automation. 373--377.
[7]
Cheng, D. I., Lin, C.-C., and Marek-Sadowska, M. 1995. Circuit partitioning with logic perturbation. In Proceedings of the International Conference on Computer Aided Design (ICCAD. 650--655.
[8]
Cormen, T. H., Leiserson, C. E., and Rivest, R. L. 1990. Introduction to Algorithms. MIT Press, Cambridge, MA.
[9]
Damiano R. and Berman, L. 1991. Dual global flow. In Proceedings of the International Conference on Computer Aided Design (ICCAD). 49--53.
[10]
De Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill. New York.
[11]
Gary D. H. and Fabio, S. 1996. Logic Synthesis and Verification Algorithms. Kluwer Academic Publishers, MA.
[12]
Jiang, Y. M., Krstic, A., Cheng, K. T., and Marek-Sadowska, M. 1998. Post-layout logic restructuring for performance optimization. In Proceedings of the 34th Conference on Design Automation. 662--665.
[13]
Kim, K. W., Liu, C. L., and Kang, S. M. 1999. Implication graph based domino logic synthesis. In Digest of the International Conference on Computer Aided Design. 111--114.
[14]
Kunz W. and Pradhan, D. K. 1994. Multi-level logic optimization by implication analysis. In Digest International Conference on Computer Aided Design. 111--114.
[15]
Kunz W. and Pradhan, D. K. 1992. Recursive learning: An attractive alternative to the decision tree for test generation for digital circuits. In Proceedings of the International Test Conference. 816--825.
[16]
Rohfleisch, B., Wurth, B., and Antreich K. 1995. Logic clause analysis for delay optimization. In Proceedings of the Design Automation Conference. 668--672.
[17]
Yuguchi, M., Nakamura, Y., Wakabayashi, K., and Fujita, T. 1995. Multi-level minimization based on multi-signal implications. In Proceedings of the Design Automation Conference. 658--662.

Cited By

View all
  • (2016)Delete‐First Rewiring TechniquesBoolean Circuit Rewiring10.1002/9781118750124.ch4(67-132)Online publication date: 8-Jan-2016
  • (2012)Almost every wire is removableProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493092(1573-1578)Online publication date: 12-Mar-2012
  • (2012)Almost every wire is removable: A modeling and solution for removing any circuit wire2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176723(1573-1578)Online publication date: Mar-2012

Index Terms

  1. Multiple wire reconnections based on implication flow graph

    Recommendations

    Comments

    Please enable JavaScript to view thecomments powered by Disqus.

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 11, Issue 4
    October 2006
    177 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/1179461
    Issue’s Table of Contents

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 01 October 2006
    Published in TODAES Volume 11, Issue 4

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. Automatic test pattern generation (ATPG)
    2. global flow optimization (GFO)
    3. implication flow graph (IFG)
    4. mandatory assignment
    5. multiple wire reconnection
    6. redundant wire

    Qualifiers

    • Article

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)1
    • Downloads (Last 6 weeks)0
    Reflects downloads up to 02 Oct 2024

    Other Metrics

    Citations

    Cited By

    View all
    • (2016)Delete‐First Rewiring TechniquesBoolean Circuit Rewiring10.1002/9781118750124.ch4(67-132)Online publication date: 8-Jan-2016
    • (2012)Almost every wire is removableProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2493092(1573-1578)Online publication date: 12-Mar-2012
    • (2012)Almost every wire is removable: A modeling and solution for removing any circuit wire2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.1109/DATE.2012.6176723(1573-1578)Online publication date: Mar-2012

    View Options

    Get Access

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media