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Logic clause analysis for delay optimization

Authors:

Berhard Rohfleisch,

Bernd Wurth,

Kurt AntreichAuthors Info & Claims

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Pages 668 - 672

https://doi.org/10.1145/217474.217608

Published: 01 January 1995 Publication History

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Cited By

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Xiaoqing Yang Wu Y(2009)Fast logic restructuring exploring fanout-reconvergent structures and extended symmetry detections2009 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2009.5250321(1113-1118)Online publication date: Jul-2009
https://doi.org/10.1109/ICCCAS.2009.5250321
Wu ZChang S(2006)Multiple wire reconnections based on implication flow graphACM Transactions on Design Automation of Electronic Systems10.1145/1179461.117946811:4(939-952)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1145/1179461.1179468
Espejo JEntrena LSan Millán EOliás EGoto S(2001)Functional extension of structural logic optimization techniquesProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370514(467-472)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370514
Show More Cited By

Index Terms

Logic clause analysis for delay optimization
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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Published In

DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

January 1995

760 pages

ISBN:0897917251

DOI:10.1145/217474

Chairman:
Bryan T. Preas
Xerox Parc, Palo Alto, CA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 January 1995

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June 12 - 16, 1995

California, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Xiaoqing Yang Wu Y(2009)Fast logic restructuring exploring fanout-reconvergent structures and extended symmetry detections2009 International Conference on Communications, Circuits and Systems10.1109/ICCCAS.2009.5250321(1113-1118)Online publication date: Jul-2009
https://doi.org/10.1109/ICCCAS.2009.5250321
Wu ZChang S(2006)Multiple wire reconnections based on implication flow graphACM Transactions on Design Automation of Electronic Systems10.1145/1179461.117946811:4(939-952)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1145/1179461.1179468
Espejo JEntrena LSan Millán EOliás EGoto S(2001)Functional extension of structural logic optimization techniquesProceedings of the 2001 Asia and South Pacific Design Automation Conference10.1145/370155.370514(467-472)Online publication date: 30-Jan-2001
https://dl.acm.org/doi/10.1145/370155.370514
Gunther WDrechsler R(2001)Performance driven optimization for MUX based FPGAsVLSI Design 2001. Fourteenth International Conference on VLSI Design10.1109/ICVD.2001.902678(311-316)Online publication date: 2001
https://doi.org/10.1109/ICVD.2001.902678
Espejo JEntrena LMillan EOlias E(2001)Functional extension of structural logic optimization techniquesProceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)10.1109/ASPDAC.2001.913352(467-472)Online publication date: 2001
https://doi.org/10.1109/ASPDAC.2001.913352
Bahar RLampe EMacii E(2000)Power optimization of technology-dependent circuits based on symbolic computation of logic implicationsACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480285:3(267-293)Online publication date: 1-Jul-2000
https://dl.acm.org/doi/10.1145/348019.348028
Al-Asaad HHayes J(2000)Logic Design Validation via Simulation and Automatic Test Pattern GenerationJournal of Electronic Testing: Theory and Applications10.1023/A:100830211824416:6(575-589)Online publication date: 1-Dec-2000
https://dl.acm.org/doi/10.1023/A%3A1008302118244
Günther WDrechsler R(2000)ACTionJournal of Systems Architecture: the EUROMICRO Journal10.1016/S1383-7621(00)00027-846:14(1321-1334)Online publication date: 1-Dec-2000
https://dl.acm.org/doi/10.1016/S1383-7621%2800%2900027-8
De Micheli G(2000)Cell-based Logic OptimizationArchitecture Design and Validation Methods10.1007/978-3-642-57199-2_2(49-87)Online publication date: 2000
https://doi.org/10.1007/978-3-642-57199-2_2
Tafertshofer PGanz AWhite JSentovich E(1999)SAT based ATPG using fast justification and propagation in the implication graphProceedings of the 1999 IEEE/ACM international conference on Computer-aided design10.5555/339492.339598(139-146)Online publication date: 7-Nov-1999
https://dl.acm.org/doi/10.5555/339492.339598
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Completeness and Redundancy in Constrained Clause Logic

Operational semantics of resolution and productivity in Horn clause logic

The need for ancestor resolution when answering queries in horn clause logic