article

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

Authors:

Hannah H. Yang,

Vijay PitchumaniAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 2

Pages 325 - 345

https://doi.org/10.1145/1142155.1142159

Published: 01 April 2006 Publication History

Abstract

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.

References

[1]

Alsarawi, S. F., Abbott, D., and Franzon, P. D. 1998. A review of 3-D packaging technology. IEEE Trans. Compon. Packag. Manufact. Tech. Part B 21, 1(Jan.), 2--14.

[2]

Banerjee, K., Souri, S. J., Kapur, P., and Saraswat, K. C. 2001. 3D-ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems on chip integration. Proc. IEEE 89, 5(May), 602--633.

[3]

Bazargan, K., Kastner, R., and Sarrafzadeh, M. 1999. 3D floorplanning: Simulated annealing and greedy placement methods for reconfigurable computing systems. In Proceedings of the 10th IEEE International Workshop on Rapid System Prototyping. 38--43.

Digital Library

[4]

Chen, G. and Sapatnekar, S. 2003. Partition-driven standard cell thermal placement. In Proceedings of the 2003 ACM International Symposium on Physical Design. Vol. 1. 75--80.

Digital Library

[5]

Cheng, L., Deng, L., and Wong D. F. 2005. Floorplanning for 3D VLSI design. In Proceedings of the 2005 ACM/IEEE Asia and South Pacific Design Automation Conference. 405--411.

Digital Library

[6]

Chu, C. N. and Wong, D. F. 1997. A matrix synthesis approach to thermal placement. In Proceedings of the 1997 ACM International Symposium on Physical Design. 163--168.

Digital Library

[7]

Cong, J. and Zhang, Y. 2005. Thermal-driven multilevel routing for 3-D ICs. In Proceedings of the 2005 ACM/IEEE Asia and South Pacific Design Automation Conference. 121--126.

Digital Library

[8]

Cong, J., Wei, J., and Zhang, Y. 2004. A thermal-driven floorplanning algorithm for 3D ICs. In Proceedings of the 2004 ACM/IEEE International Conference on Computer Aided Design. 306--313.

Digital Library

[9]

Das, S., Fan, A., and Chen, K. N. 2004. Technology, performance, and computer-aided design of three-dimensional integrated circuits. In Proceedings of the 2004 ACM International Symposium on Physical Design. 108--115.

Digital Library

[10]

Deng, Y. and Maly, W. P. 2001. Interconnect characteristics of 2.5-D system integration scheme. In Proceedings of the 2001 ACM International Symposium on Physical Design. 171--175.

Digital Library

[11]

Eisenmann, H. and Johannes, F. M. 1998. Generic global placement and floorplanning. In Proceedings of the 1998 ACM/IEEE Design Automation Conference. 269--274.

Digital Library

[12]

Goplen, B. and Sapatnekar, S. 2003. Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In Proceedings of the 2003 ACM/IEEE International Conference on Computer Aided Design. 86--89.

Digital Library

[13]

Goplen, B. and Sapatnekar, S. 2005. Thermal via placement in 3D ICs. In Proceedings of the 2005 ACM International Symposium on Physical Design. 167--174.

Digital Library

[14]

Hong, X. L., Huang, G., Cai, Y., Gu, J., Dong, S., Cheng, C. K., and Gu, J. 2000. Corner block list: An effective and efficient topological representation of non-slicing floorplan. In Proceedings of the 2000 ACM/IEEE International Conference on Computer Aided Design. 8--12.

Digital Library

[15]

Lall, B., Ortega, A., and Kabir, H. 1994. Thermal design rules for electronic components on conducting boards in passively cooled enclosures. In Proceedings of the 1994 Inter-Society Conference on Thermal Phenomena. 50--61.

[16]

Li, Z., Hong, X. L., Zhou, Q., Cai, Y., Bian, J., Yang, H., Saxena, P., and Pitchumani, V. 2005. A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. In Proceedings of the 2005 IEEE International Symposium on Circuits and Systems. Vol. 6. 230--233.

[17]

Lou, J., Thakur, S., Krishnamoorthy, S., and Sheng, H. S. 2002. Estimating routing congestion using probabilistic analysis. IEEE Trans. Comput. Aid. Des. 21, 1(Jan.), 32--41.

Digital Library

[18]

Shiu, P. H., Ravichandran, R., Easwar, S., and Lim, S. K. 2004. Multi-layer floorplanning for reliable sytem-on-package. In Proceedings of the 2004 IEEE International Symposium on Circuits and Systems. Vol. 5. 69--72.

[19]

Tsai, C. H. and Kang, S. M. 2000. Cell-level placement for improving substrate thermal distribution. IEEE Trans. Comput. Aid. Des. 19, 2(Feb.), 253--266.

Digital Library

[20]

Wang, T. Y., Lee, Y. M., and Chen, C. P. 2003. 3D-thermal-ADI: Efficient chip-level transient thermal simulator. In Proceedings of the 2003 ACM International Symposium on Physical Design. 10--17.

Digital Library

[21]

Yamazaki, H., Sakanushi, K., Nakatake, S., and Kajitani, Y. 2000. The 3D-packing by meta data structure and packing heuristics. IEICE Trans. Fundament. Electron. Commun. Comput. Sci. E83-A, 4(Apr.), 639--645.

Cited By

Yuan ZDing DZhang W(2023)Effect of Thermal via Design on Heat Dissipation of High-Lead QFN Packages Mounted on PCBApplied Sciences10.3390/app13231265313:23(12653)Online publication date: 24-Nov-2023
https://doi.org/10.3390/app132312653
Salah K(2017)Survey on 3D-ICs thermal modeling, analysis, and management techniques2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)10.1109/EPTC.2017.8277428(1-4)Online publication date: Dec-2017
https://doi.org/10.1109/EPTC.2017.8277428
Lu H(2014)Linear-Time Compression of Bounded-Genus Graphs into Information-Theoretically Optimal Number of BitsSIAM Journal on Computing10.1137/12087914243:2(477-496)Online publication date: Jan-2014
https://doi.org/10.1137/120879142
Show More Cited By

Index Terms

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

Recommendations

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning

In this paper, we investigate thermal via (T-via) planning during three-dimensional (3-D) floorplanning. First, we consider the temperature constrained T-via planning (TVP) problem on a given 3-D floorplan. Second, we integrate dynamic TVP into 3-D ...
Integrating dynamic thermal via planning with 3D floorplanning algorithm
ISPD '06: Proceedings of the 2006 international symposium on Physical design

Incorporating thermal vias into 3D ICs is a promising way to reduce circuit temperature by lowering down the thermal resistances between device layers. In this paper, we integrate dynamic thermal via planning into 3D floorplanning process. Our 3D ...
Power-density aware floorplanning for reducing maximum on-chip temperature
MS '07: The 18th IASTED International Conference on Modelling and Simulation

With microprocessor power densities escalating rapidly as technology scales below 100nm level, there is an urgent need for developing innovative cooling solutions. In this paper, we introduce the concept of power-density aware thermal floorplanning and ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 2

April 2006

283 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1142155

Issue’s Table of Contents

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2006

Published in TODAES Volume 11, Issue 2

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

17
Total Citations
View Citations
729
Total Downloads

Downloads (Last 12 months)10
Downloads (Last 6 weeks)3

Reflects downloads up to 23 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Yuan ZDing DZhang W(2023)Effect of Thermal via Design on Heat Dissipation of High-Lead QFN Packages Mounted on PCBApplied Sciences10.3390/app13231265313:23(12653)Online publication date: 24-Nov-2023
https://doi.org/10.3390/app132312653
Salah K(2017)Survey on 3D-ICs thermal modeling, analysis, and management techniques2017 IEEE 19th Electronics Packaging Technology Conference (EPTC)10.1109/EPTC.2017.8277428(1-4)Online publication date: Dec-2017
https://doi.org/10.1109/EPTC.2017.8277428
Lu H(2014)Linear-Time Compression of Bounded-Genus Graphs into Information-Theoretically Optimal Number of BitsSIAM Journal on Computing10.1137/12087914243:2(477-496)Online publication date: Jan-2014
https://doi.org/10.1137/120879142
Kandlikar S(2014)Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated CircuitsJournal of Electronic Packaging10.1115/1.4027175136:2(024001)Online publication date: 29-Apr-2014
https://doi.org/10.1115/1.4027175
Salah KAbdelSalam M(2013)Emerging reconfigurable systems: Exploring 3D FPGA architectures2013 25th International Conference on Microelectronics (ICM)10.1109/ICM.2013.6734947(1-4)Online publication date: Dec-2013
https://doi.org/10.1109/ICM.2013.6734947
Ebrahimi MDaneshtalab MLiljeberg PPlosila JTenhunen H(2013)Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architectureJournal of Computer and System Sciences10.1016/j.jcss.2012.09.00579:4(475-491)Online publication date: 1-Jun-2013
https://dl.acm.org/doi/10.1016/j.jcss.2012.09.005
Pasricha S(2012)A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-ChipProceedings of the 2012 25th International Conference on VLSI Design10.1109/VLSID.2012.82(268-273)Online publication date: 7-Jan-2012
https://dl.acm.org/doi/10.1109/VLSID.2012.82
Knechtel JMarkov ILienig J(2012)Assembling 2-D Blocks Into 3-D ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217464031:2(228-241)Online publication date: 1-Feb-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2174640
Knechtel J(2012)Nutzung von klassischen IP-Blöcken in 3D-SchaltkreisenEntwurf integrierter 3D-Systeme der Elektronik10.1007/978-3-642-30572-6_9(145-174)Online publication date: 12-Sep-2012
https://doi.org/10.1007/978-3-642-30572-6_9
Neubert H(2012)Thermische Herausforderungen und ihre Berücksichtigung beim 3D-EntwurfEntwurf integrierter 3D-Systeme der Elektronik10.1007/978-3-642-30572-6_11(191-206)Online publication date: 12-Sep-2012
https://doi.org/10.1007/978-3-642-30572-6_11
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents