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Hideo Ohno
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2020 – today
- 2023
- [i5]Shuvro Chowdhury, Andrea Grimaldi
, Navid Anjum Aadit, Shaila Niazi, Masoud Mohseni, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Luke Theogarajan, Giovanni Finocchio, Supriyo Datta, Kerem Yunus Çamsari
A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms. CoRR abs/2302.06457 (2023) - [i4]Keito Kobayashi, Nihal Singh, Qixuan Cao, Kemal Selcuk, Tianrui Hu, Shaila Niazi, Navid Anjum Aadit, Shun Kanai, Hideo Ohno, Shunsuke Fukami, Kerem Yunus Çamsari:
CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning. CoRR abs/2304.05949 (2023) - [i3]Kemal Selcuk, Shun Kanai, Rikuto Ota, Hideo Ohno, Shunsuke Fukami, Kerem Yunus Çamsari:
Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets. CoRR abs/2311.06642 (2023) - 2021
- [j20]Masanori Natsui
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - [i2]Jan Kaiser
Hardware-aware in-situ Boltzmann machine learning using stochastic magnetic tunnel junctions. CoRR abs/2102.05137 (2021) - 2020
- [c17]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2 - [i1]Kerem Yunus Çamsari, Mustafa Mert Torunbalci, William A. Borders, Hideo Ohno, Shunsuke Fukami:
Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits. CoRR abs/2012.06950 (2020)
2010 – 2019
- 2019
- [j19]Masanori Natsui
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [j18]William A. Borders, Ahmed Zeeshan Pervaiz, Shunsuke Fukami
Integer factorization using stochastic magnetic tunnel junctions. Nat. 573(7774): 390-393 (2019) - [c16]Masanori Natsui
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - 2016
- [j17]Tetsuo Endoh, Hiroki Koike, Shoji Ikeda
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 109-119 (2016) - [j16]Hideo Ohno
Spintronics [Scanning the Issue]. Proc. IEEE 104(10): 1782-1786 (2016) - [j15]Takahiro Hanyu
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c15]Masanori Natsui
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - 2015
- [j14]Masanori Natsui
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - [c14]Daisuke Suzuki, Masanori Natsui
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - 2014
- [j13]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j12]Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11(3): 20131006 (2014) - [j11]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j10]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [c13]Shunsuke Fukami
Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. ASP-DAC 2014: 684-691 - [c12]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c11]Noboru Sakimura, Yukihide Tsuji
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - 2013
- [j9]Daisuke Suzuki, Masanori Natsui
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013) - [j8]Takashi Ohsawa
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48(6): 1511-1520 (2013) - [c10]Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j7]Takayuki Kawahara
Spin-transfer torque RAM technology: Review and prospect. Microelectron. Reliab. 52(4): 613-627 (2012) - [c9]Shoun Matsunaga, Masanori Natsui
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476 - [c8]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c7]Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. VLSIC 2012: 44-45 - [c6]Takashi Ohsawa
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC 2012: 46-47 - 2010
- [j6]Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Trans. Electron. 93-C(5): 602-607 (2010) - [j5]Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Trans. Electron. 93-C(5): 608-613 (2010) - [j4]Riichiro Takemura, Takayuki Kawahara
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. IEEE J. Solid State Circuits 45(4): 869-879 (2010)
2000 – 2009
- 2009
- [c5]Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435 - 2008
- [j3]Takayuki Kawahara
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. IEEE J. Solid State Circuits 43(1): 109-120 (2008) - 2007
- [c4]Takayuki Kawahara
SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. ICECS 2007: 1011-1014 - [c3]Takayuki Kawahara
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. ISSCC 2007: 480-617 - 2004
- [c2]Fumihiro Matsukura, Daichi Chiba
Electrical Magnetization Reversal in Ferromagnetic Semiconductors. ICMENS 2004: 128
1990 – 1999
- 1997
- [j2]Yuichi Kado
An ultralow power CMOS/SIMOX programmable counter LSI. IEEE J. Solid State Circuits 32(10): 1582-1587 (1997) - [j1]Kiyoharu Aizawa, Hideo Ohno, Yuichiro Egi, Takayuki Hamamoto
On sensor image compression. IEEE Trans. Circuits Syst. Video Technol. 7(3): 543-548 (1997) - 1994
- [c1]Kiyoharu Aizawa, Hideo Ohno, Takayuki Hamamoto
A Novel Image Sensor for Video Compression. ICIP (3) 1994: 591-595
Coauthor Index
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