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Tetsuo Endoh
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2020 – today
- 2024
- [j55]Li Zhang
, Tao Li
Small Area and High Throughput Error Correction Module of STT-MRAM for Object Recognition Systems. IEEE Trans. Ind. Informatics 20(5): 7777-7786 (2024) - 2023
- [j54]Tao Li
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3. Neural Comput. Appl. 35(15): 11013-11041 (2023) - [j53]Tao Li
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society. IEEE Trans. Ind. Informatics 19(8): 8953-8964 (2023) - [j52]Tao Li
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". IEEE Trans. Very Large Scale Integr. Syst. 31(6): 906 (2023) - [j51]Tao Li
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 1078-1082 (2023) - 2022
- [j50]Tao Li
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18(5): 3055-3065 (2022) - [c21]K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. IRPS 2022: 54-1 - 2021
- [j49]Masanori Natsui
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - 2020
- [j48]Tao Li
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application. IEEE Access 8: 9403-9419 (2020) - [j47]Tao Li
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate. IEEE Access 8: 142931-142955 (2020) - [j46]Tao Li
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering. IEEE Trans. Veh. Technol. 69(9): 9330-9341 (2020) - [c20]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j45]Masanori Natsui
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [c19]Masanori Natsui
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - [c18]Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda
A novel memory test system with an electromagnet for STT-MRAM testing. NVMTS 2019: 1-4 - 2018
- [c17]Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh:
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. NVMTS 2018: 1-5 - 2017
- [c16]Tetsuo Endoh:
Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs. VLSI-DAT 2017: 1-3 - 2016
- [j44]Tetsuo Endoh, Hiroki Koike, Shoji Ikeda
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 109-119 (2016) - [j43]Soshi Sato, Kikuo Yamabe, Tetsuo Endoh, Masaaki Niwa:
Formation mechanism of concave by dielectric breakdown on silicon carbide metal-oxide-semiconductor capacitor. Microelectron. Reliab. 58: 185-191 (2016) - [j42]Takahiro Hanyu
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c15]Masanori Natsui
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - 2015
- [j41]Masanori Natsui
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50(2): 476-489 (2015) - [c14]Tetsuo Endoh:
Nonvolatile logic and memory devices based on spintronics. ISCAS 2015: 13-16 - [c13]Daisuke Suzuki, Masanori Natsui
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC 2015: 172- - 2014
- [j40]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j39]Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11(3): 20131006 (2014) - [j38]Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11(10): 20140297 (2014) - [j37]Daisuke Suzuki, Noboru Sakimura, Masanori Natsui
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11(13): 20140296 (2014) - [j36]Satoru Tanoi, Tetsuo Endoh:
A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs. IEICE Trans. Electron. 97-C(5): 423-430 (2014) - [j35]Kazuki Itoh, Tetsuo Endoh:
A Novel Alternating Voltage Controlled Current Sensing Method for Suppressing Thermal Dependency. IEICE Trans. Electron. 97-C(5): 431-437 (2014) - [c12]Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo
A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. ISCAS 2014: 1588-1591 - [c11]Noboru Sakimura, Yukihide Tsuji
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. ISSCC 2014: 184-185 - 2013
- [j34]Daisuke Suzuki, Masanori Natsui
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10(23): 20130772 (2013) - [j33]Tetsuo Endoh:
Foreword. IEICE Trans. Electron. 96-C(5): 619 (2013) - [j32]Hyoungjun Na, Tetsuo Endoh:
A High Performance Current Latch Sense Amplifier with Vertical MOSFET. IEICE Trans. Electron. 96-C(5): 655-662 (2013) - [j31]Takashi Ohsawa
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48(6): 1511-1520 (2013) - [c10]Yitao Ma, Tadashi Shibata, Tetsuo Endoh:
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. ISCAS 2013: 1248-1251 - [c9]Masanori Natsui
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC 2013: 194-195 - 2012
- [j30]Hyoungjun Na, Tetsuo Endoh:
Current Controlled MOS Current Mode Logic with Auto-Detection of Threshold Voltage Fluctuation. IEICE Trans. Electron. 95-C(4): 617-626 (2012) - [j29]Hyoungjun Na, Tetsuo Endoh:
A Schmitt Trigger Based SRAM with Vertical MOSFET. IEICE Trans. Electron. 95-C(5): 792-801 (2012) - [j28]Takuya Imamoto, Tetsuo Endoh:
Source/Drain Engineering for High Performance Vertical MOSFET. IEICE Trans. Electron. 95-C(5): 807-813 (2012) - [j27]Yuto Norifusa, Tetsuo Endoh:
Evaluation of Performance in Vertical 1T-DRAM and Planar 1T-DRAM. IEICE Trans. Electron. 95-C(5): 847-853 (2012) - [j26]Shuta Togashi, Takashi Ohsawa
Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating. IEICE Trans. Electron. 95-C(5): 854-859 (2012) - [j25]Moon-Sik Seo, Tetsuo Endoh:
FG Width Scalability of the 3-D Vertical FG NAND Using the Sidewall Control Gate (SCG). IEICE Trans. Electron. 95-C(5): 891-897 (2012) - [c8]Shoun Matsunaga, Masanori Natsui
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC 2012: 475-476 - [c7]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c6]Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. VLSIC 2012: 44-45 - [c5]Takashi Ohsawa
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC 2012: 46-47 - 2011
- [j24]Moon-Sik Seo, Tetsuo Endoh:
The Optimum Physical Targets of the 3-Dimensional Vertical FG NAND Flash Memory Cell Arrays with the Extended Sidewall Control Gate (ESCG) Structure. IEICE Trans. Electron. 94-C(5): 686-692 (2011) - [j23]Yuto Norifusa, Tetsuo Endoh:
Impact of Floating Body Type DRAM with the Vertical MOSFET. IEICE Trans. Electron. 94-C(5): 705-711 (2011) - [j22]Takuya Imamoto, Takeshi Sasaki, Tetsuo Endoh:
Evaluation of 1/f Noise Characteristics in High-k/Metal Gate and SiON/Poly-Si Gate MOSFET with 65 nm CMOS Process. IEICE Trans. Electron. 94-C(5): 724-729 (2011) - [j21]Masakazu Muraguchi, Yoko Sakurai, Yukihiro Takada, Shintaro Nomura, Kenji Shiraishi, Mitsuhisa Ikeda, Katsunori Makihara, Seiichi Miyazaki, Yasuteru Shigeta
Study on Collective Electron Motion in Si-Nano Dot Floating Gate MOS Capacitor. IEICE Trans. Electron. 94-C(5): 730-736 (2011) - [j20]Masakazu Muraguchi, Tetsuo Endoh:
Study on Impurity Distribution Dependence of Electron-Dynamics in Vertical MOSFET. IEICE Trans. Electron. 94-C(5): 737-742 (2011) - [j19]Tetsuo Endoh, Masashi Kamiyanagi, Masakazu Muraguchi, Takuya Imamoto, Takeshi Sasaki:
The Impact of Current Controlled-MOS Current Mode Logic/Magnetic Tunnel Junction Hybrid Circuit for Stable and High-Speed Operation. IEICE Trans. Electron. 94-C(5): 743-750 (2011) - [j18]Takeshi Sasaki, Takuya Imamoto, Tetsuo Endoh:
Temperature Dependency of Driving Current in High-k/Metal Gate MOSFET and Its Influence on CMOS Inverter Circuit. IEICE Trans. Electron. 94-C(5): 751-759 (2011) - [j17]Masashi Kamiyanagi, Takuya Imamoto, Takeshi Sasaki, Hyoungjun Na, Tetsuo Endoh:
Verification of Stable Circuit Operation of 180 nm Current Controlled MOS Current Mode Logic under Threshold Voltage Fluctuation. IEICE Trans. Electron. 94-C(5): 760-766 (2011) - [c4]Yitao Ma, Tetsuo Endoh, Tadashi Shibata:
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. ISOCC 2011: 203-206 - 2010
- [j16]Tetsuo Endoh, Koji Sakui, Yukio Yasuda:
Design of 30 nm FinFETs and Double Gate MOSFETs with Halo Structure. IEICE Trans. Electron. 93-C(5): 534-539 (2010) - [j15]Masakazu Muraguchi, Tetsuo Endoh:
Study on Quantum Electro-Dynamics in Vertical MOSFET. IEICE Trans. Electron. 93-C(5): 552-556 (2010) - [j14]Tetsuo Endoh, Koji Sakui, Yukio Yasuda:
Sub-10 nm Multi-Nano-Pillar Type Vertical MOSFET. IEICE Trans. Electron. 93-C(5): 557-562 (2010) - [j13]Masakazu Muraguchi, Yukihiro Takada, Shintaro Nomura, Tetsuo Endoh, Kenji Shiraishi:
Importance of the Electronic State on the Electrode in Electron Tunneling Processes between the Electrode and the Quantum Dot. IEICE Trans. Electron. 93-C(5): 563-568 (2010) - [j12]Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda
Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. IEICE Trans. Electron. 93-C(5): 602-607 (2010) - [j11]Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda
Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. IEICE Trans. Electron. 93-C(5): 608-613 (2010) - [c3]Koji Sakui, Tetsuo Endoh:
A compact and low power logic design for multi-pillar vertical MOSFETs. ISCAS 2010: 309-312
2000 – 2009
- 2009
- [j10]Tetsuo Endoh, Yuto Norifusa:
Scalability of Vertical MOSFETs in Sub-10 nm Generation and Its Mechanism. IEICE Trans. Electron. 92-C(5): 594-597 (2009) - [j9]Tetsuo Endoh, Yuto Norifusa:
Study of Self-Heating Phenomena in Si Nano Wire MOS Transistor. IEICE Trans. Electron. 92-C(5): 598-602 (2009) - [j8]Tetsuo Endoh, Masashi Kamiyanagi:
Novel Concept Dynamic Feedback MCML Technique for High-Speed and High-Gain MCML Type Latch. IEICE Trans. Electron. 92-C(5): 603-607 (2009) - [c2]Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE 2009: 433-435 - 2007
- [j7]Tetsuo Endoh, Kazuyuki Hirose, Kenji Shiraishi:
Physical Origin of Stress-Induced Leakage Currents in Ultra-Thin Silicon Dioxide Films. IEICE Trans. Electron. 90-C(5): 955-961 (2007) - [j6]Tetsuo Endoh, Yuto Momma:
Study of 30-nm Double-Gate MOSFET with Halo Implantation Technology Using a Two-Dimensional Device Simulator. IEICE Trans. Electron. 90-C(5): 1000-1005 (2007) - 2001
- [j5]Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. IEEE J. Solid State Circuits 36(1): 34-39 (2001) - [j4]Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka:
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid State Circuits 36(6): 988-996 (2001) - [c1]Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator. ASP-DAC 2001: 297-301
1990 – 1999
- 1999
- [j3]Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka:
New three-dimensional memory array architecture for future ultrahigh-density DRAM. IEEE J. Solid State Circuits 34(4): 476-483 (1999) - 1993
- [j2]Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka:
Reliability issues of flash memory cells. Proc. IEEE 81(5): 776-788 (1993)
1980 – 1989
- 1989
- [j1]Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka:
An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. IEEE J. Solid State Circuits 24(5): 1238-1243 (1989)
Coauthor Index
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