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Shogo Nakaya
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2010 – 2019
- 2013
- [j3]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. Inf. Media Technol. 8(2): 262-269 (2013) - [j2]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 6: 52-59 (2013) - [c8]Shogo Nakaya, Yuichi Nakamura:
Adaptive sensing of ECG signals using R-R interval prediction. EMBC 2013: 9-12 - 2012
- [j1]Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura, Tadahiko Sugibayashi:
A non-volatile reconfigurable offloader for wireless sensor nodes. SIGARCH Comput. Archit. News 40(5): 87-92 (2012) - 2011
- [c7]Makoto Miyamura, Shogo Nakaya, Munehiro Tada
, Toshitsugu Sakamoto, Koichiro Okamoto, Naoki Banno, Shinji Ishida, Kimihiko Ito, Hiromitsu Hada, Noboru Sakimura, Tadahiko Sugibayashi, Masato Motomura
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS. ISSCC 2011: 228-229
2000 – 2009
- 2001
- [c6]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Arithmetic Operation Oriented Reconfigurable Chip: RHW. FPL 2001: 618-622 - 2000
- [c5]Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara:
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHW. FCCM 2000: 281-282
1990 – 1999
- 1998
- [c4]Hidenori Sakanashi, Mehrdad Salami, Masaya Iwata, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Tetsuya Higuchi:
Evolvable Hardware Chip for High Precision Printer Image Compression. AAAI/IAAI 1998: 486-491 - [c3]Isamu Kajitani, Tsutomu Hoshino, Daisuke Nishikawa, Hiroshi Yokoi, Shogo Nakaya, Tsukasa Yamauchi, Takeshi Inuo, Nobuki Kajihara, Masaya Iwata, Didier Keymeulen, Tetsuya Higuchi:
A Gate-Level EHW Chip: Implementing GA Operations and Reconfigurable Hardware on a Single LSI. ICES 1998: 1-12 - 1996
- [c2]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. FCCM 1996: 148-156 - [c1]Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: An Adaptive Massively Parallel Computer and its Control-Data-Flow Based Compiling Method. Parcella 1996: 128-136
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