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Michael Choi
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2020 – today
- 2024
- [j13]Dong-Hun Lee
, Kent Edrian Lozada
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. IEEE J. Solid State Circuits 59(10): 3232-3241 (2024) - [j12]Jihun Choi, Sangwook Na, Hojin Kim, Hyungdong Roh, Youngjae Cho, Michael Choi, Min-Seong Choo, Jeongjin Roh:
High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4613-4617 (2024) - [c29]Rafael F. Rincon, Lynn M. Carter, David M. Hollibaugh-Baker, Cornelis F. Du Toit, Martin Perrine, Peter Steigner, Babak Farrokh, Michael Choi, Steve Van Nostrand, Nga Cao, Emileigh Shoemaker:
Space Exploration Synthetic Aperture Radar - Lunar Investigations Targeted Experiment (SESAR-LITE). IGARSS 2024: 6294-6298 - [c28]Sangheon Lee, Jinwoo Park, Junsang Park, Sangkyu Lee, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
3.9 A 1.2V High-Voltage-Tolerant Bootstrapped Analog Sampler in 12-bit SAR ADC Using 3nm GAA's 0.7V Thin-Gate-Oxide Transistor. ISSCC 2024: 70-72 - [c27]Byeongwoo Koo, Sunghan Do, Sangkyu Lee, Sang-Pil Nam, Heewook Shin, Saemin Im, Hyochul Shin, Sungno Lee, Junsang Park, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2 - [c26]Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. VLSI Technology and Circuits 2024: 1-2 - [c25]Junsang Park, Jinwoo Park, Jaemin Hong, Sun-Jae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyung-Hoon Lee, Byeongwoo Koo, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j11]Timothy O. Dickson
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. IEEE J. Solid State Circuits 58(4): 1074-1086 (2023) - [c24]Kent Edrian Lozada
A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. A-SSCC 2023: 1-3 - [c23]Jusung Lee, Youngwoo Jo, Wonsik Yu, WooSeok Kim, Michael Choi, Sanghune Park, Jongshin Shin:
A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. CICC 2023: 1-2 - 2022
- [j10]Yulan Guo
Soft Exemplar Highlighting for Cross-View Image-Based Geo-Localization. IEEE Trans. Image Process. 31: 2094-2105 (2022) - [c22]Woojoong Jung, Minsu Kim, Hyunjun Park, Sungmin Yoo, Tae-Hwang Kong, Jun-Hyeok Yang, Michael Choi, Jongshin Shin, Hyung-Min Lee
A Hybrid Always-Dual-Path Recursive Step-Down Converter Using Adaptive Switching Level Control Achieving 95.4% Efficiency with 288mΩ Large-DCR Inductor. CICC 2022: 1-2 - [c21]Dokyung Lim, Sounghun Shin, Seungmin Lee, Kihyun Kwon, Jeongmin An, Wonsik Yu, Chanyoung Jeong, WooSeok Kim, Michael Choi, Jongshin Shin:
Clock Generator with IS026262 ASIL-D Grade Safety Mechanism for SoC Clocking Application. ISSCC 2022: 210-212 - [c20]Junghyun Park, Jooseong Kim, Kwangho Kim, Jun-Hyeok Yang, Michael Choi, Jongshin Shin:
A 0.65V 1316µm2Fully Synthesizable Digital Temperature Sensor Using Wire Metal Achieving O.16nJ.%2-Accuracy FoM in 5nm FinFET CMOS. ISSCC 2022: 220-222 - [c19]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, Marcel A. Kossel, Thomas Morf, Young-Ho Choi, Pier Andrea Francese
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. VLSI Technology and Circuits 2022: 28-29 - [c18]Byeongwoo Koo, Sunghan Do, Sang-Pil Nam, Heewook Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jung-Ho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 86-87 - [c17]Kyung-Hoon Lee, Jinwoo Park, Younghyo Park, Byeongwoo Koo, Sunghan Do, Woongtaek Lim, Sungno Lee, Hyochul Shin, Eunhye Oh, Youngjae Cho, Michael Choi, Jongshin Shin:
An Automotive ASIL-D Safety Mechanism in ADC and DAC for Communication Application. VLSI Technology and Circuits 2022: 142-143 - [c16]Serdar S. Yonar, Pier Andrea Francese
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - [c15]Kyoung-Jun Moon, Dong-Ryeol Oh
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 172-173 - 2021
- [j9]Dong-Jin Chang
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. IEEE J. Solid State Circuits 56(9): 2691-2700 (2021) - [c14]Seung-Yong Lim, Raymond Mabilangan, Dong-Jin Chang, Young-Jae Cho, Michael Choi, Seung-Tak Ryu:
An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. A-SSCC 2021: 1-3 - [c13]Rafael F. Rincon, Lynn M. Carter
Recent Developments of the Space Exploration Synthetic Aperture Radar (SESAR) for Planetary Science Missions. IGARSS 2021: 7839-7842 - [c12]Seung-Yeob Baek, Il-Hoon Jang, Michael Choi, Hyungdong Roh, Woongtaek Lim, Youngjae Cho, Jongshin Shin:
A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. ISSCC 2021: 172-174 - [c11]Dong-Hoon Jung, Tae-Hwang Kong, Jun-Hyeok Yang, SangHo Kim, Kwangho Kim, Jeongpyo Park, Michael Choi, Jongshin Shin:
29.6 A Distributed Digital LDO with Time-Multiplexing Calibration Loop Achieving 40A/mm2 Current Density and 1mA-to-6.4A Ultra-Wide Load Range in 5nm FinFET CMOS. ISSCC 2021: 414-416 - 2020
- [j8]Kyoung-Jun Moon
A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. IEEE Trans. Circuits Syst. 67-II(12): 2843-2847 (2020) - [c10]Byoung-Joo Yoo, Dong-Hyuk Lim, Hyonguk Pang, June-Hee Lee, Seung-Yeob Baek, Naxin Kim, Dong-Ho Choi, Young-Ho Choi, Hyeyeon Yang, Taehun Yoon, Sang-Hyeok Chu, Kangjik Kim, Woochul Jung, Bong-Kyu Kim, Jaechol Lee, Gunil Kang, Sang-Hune Park, Michael Choi, Jongshin Shin:
6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. ISSCC 2020: 122-124 - [c9]Min-Woo Ko, Gyeong-Gu Kang, Ki-Duk Kim, Ji-Hun Lee, Seok-Tae Koh, Tae-Hwang Kong, Sang-Ho Kim, Sungyong Lee, Michael Choi, Jongshin Shin, Gyu-Hyeong Cho, Hyunsik Kim:
11.8 A 96.8%-Efficiency Continuous Input/Output-Current Step-Up/Down Converter Powering Disposable IoTs with Reconfigurable Multi-Cell-Balanced Alkaline Batteries. ISSCC 2020: 204-206
2010 – 2019
- 2019
- [j7]Kyoung-Jun Moon
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. IEEE J. Solid State Circuits 54(9): 2532-2542 (2019) - 2018
- [j6]Michael Choi
Imperfect information transmission and adverse selection in asset markets. J. Econ. Theory 176: 619-649 (2018) - [j5]Il-Hoon Jang
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. IEEE J. Solid State Circuits 53(4): 1139-1148 (2018) - [c8]Kyung-Hoon Lee, Sang-Pil Nam, Jung-Ho Lee, Michael Choi, Hyung-Jong Ko, San-Ho Byun, Jin-chul Lee, Yong-Hoon Lee, Yeong-Cheol Rhee, Yoon-Kyung Choi, Byunghoon Kang, Changbyung Park, Sungsoo Park, Taesung Kim:
A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses. ISSCC 2018: 184-186 - 2017
- [j4]Michael Choi
Ordinal aggregation results via Karlin's variation diminishing property. J. Econ. Theory 168: 1-11 (2017) - 2015
- [j3]Hyeok-Ki Hong, Wan Kim
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. IEEE J. Solid State Circuits 50(2): 543-555 (2015) - 2014
- [c7]Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Ho-Jin Park, Gyoocheol Hwang:
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation. VLSIC 2014: 1-2 - 2013
- [c6]Hyeok-Ki Hong, Hyun-Wook Kang, Barosaim Sung, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, Seung-Tak Ryu:
An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. ISSCC 2013: 470-471 - 2012
- [c5]Hyeok-Ki Hong, Wan Kim
A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. CICC 2012: 1-4 - [c4]Michael Choi, Woon Tiong Ang, Jie Chen:
Close-proximity, real-time thermoacoustic sensors: Design, characterization, and testing. ISCAS 2012: 3102-3105 - 2010
- [c3]Young-Ju Kim, Kyung-Hoon Lee, Seung-Hak Ji, Yi-Gi Kwon, Seung-Hoon Lee, Kyoung-Jun Moon, Michael Choi, Ho-Jin Park, Byeong-Ha Park:
A 10b 120MS/s 45nm CMOS ADC using A re-configurable three-stage switched op-amp. CICC 2010: 1-4
2000 – 2009
- 2009
- [c2]Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park:
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. CICC 2009: 271-274 - 2006
- [c1]Sandeep Gupta, Michael Choi, Michael A. Inerfield, Jingbo Wang:
A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS. ISSCC 2006: 2360-2369 - 2001
- [j2]Michael Choi, Asad A. Abidi:
A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS. IEEE J. Solid State Circuits 36(12): 1847-1858 (2001) - 2000
- [j1]Hui Pan
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR. IEEE J. Solid State Circuits 35(12): 1769-1780 (2000)
Coauthor Index
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last updated on 2024-11-15 20:38 CET by the dblp team
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