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"A 5.3-GB/s embedded SDRAM core with slight-boost scheme."

Akira Yamazaki et al. (1999)

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DOI: 10.1109/4.760377

access: closed

type: Journal Article

metadata version: 2022-10-02

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  - journals/jssc/YamazakiYHMHTMY99
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  - https://dblp.org/rec/journals/jssc/YamazakiYHMHTMY99
Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada:
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34(5): 661-669 (1999)

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