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Hideyuki Ozaki
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2000 – 2009
- 2005
- [j14]Akira Yamazaki, Fukashi Morishita
, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara:
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. 88-C(10): 2020-2027 (2005) - 2003
- [j13]Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki:
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2991-3000 (2003) - 2001
- [j12]Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara:
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36(1): 46-54 (2001) - 2000
- [j11]Tadaaki Yamauchi, Fukashi Morishita
High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits 35(8): 1169-1178 (2000) - [j10]Takashi Kono, Takeshi Hamamoto, Katsuyoshi Mitsui, Yasuhiro Konishi, Tsutomu Yoshihara, Hideyuki Ozaki:
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. IEEE J. Solid State Circuits 35(8): 1179-1185 (2000) - [j9]Shigehiro Kuge, Tetsuo Kato, Kiyohiro Furutani, Shigeru Kikuda, Katsuyoshi Mitsui, Takeshi Hamamoto, Jun Setogawa, Kei Hamade, Yuichiro Komiya, Satoshi Kawasaki, Takashi Kono, Teruhiko Amano, Takashi Kubo, Masaru Haraguchi, Yoshito Nakaoka, Mihoko Akiyama, Yasuhiro Konishi, Hideyuki Ozaki, Tsutomu Yoshihara:
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. IEEE J. Solid State Circuits 35(11): 1680-1689 (2000)
1990 – 1999
- 1998
- [j8]Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada:
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33(5): 770-778 (1998) - 1996
- [j7]Tadaaki Yamauchi, Yoshikazu Morooka, Hideyuki Ozaki:
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory. IEEE J. Solid State Circuits 31(4): 523-530 (1996) - [j6]Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mikio Asakura, Kenichi Yasuda, Kiyohiro Furutani, Tetsuo Kato, Hideto Hidaka, Hideyuki Ozaki:
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. IEEE J. Solid State Circuits 31(4): 575-585 (1996) - [j5]Takeshi Hamamoto, Yoshikazu Maroaka, Mikio Asakura, Hideyuki Ozaki:
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. IEEE J. Solid State Circuits 31(4): 592-601 (1996) - 1995
- [j4]Tsukasa Ooishi, Yuichiro Komiya, Kei Hamade, Mho Asakura, Kenichi Yasuda, Kiyohiro Furutani, Hideto Hidaka, Hiroshi Miyamoto, Hideyuki Ozaki:
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. IEEE J. Solid State Circuits 30(4): 471-479 (1995) - 1994
- [j3]Kiyohiro Furutani, Hiroshi Miyamoto, Yoshikazu Morooka, M. Suwa, Hideyuki Ozaki:
An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM. IEEE J. Solid State Circuits 29(3): 308-310 (1994) - [j2]Yasuhiko Tsukikawa, Takeshi Kajimoto, Yasuhiko Okasaka, Yoshikazu Morooka, Kiyohiro Furutani, Hiroshi Miyamoto, Hideyuki Ozaki:
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs. IEEE J. Solid State Circuits 29(4): 534-538 (1994)
1980 – 1989
- 1989
- [j1]Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima:
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. IEEE J. Solid State Circuits 24(1): 43-49 (1989) - 1986
- [c1]Yasumasa Nishimura, Mitsuhiro Hamada, Hideto Hidaka, Hideyuki Ozaki, Kazuyasu Fujishima, Y. Hayasaka:
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. ITC 1986: 826-829
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