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Jooheung Lee
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2020 – today
- 2024
- [j17]Hyeonjun Shin, Jooheung Lee
:
Hardware Multi-Threaded System for High-Performance JPEG Decoding. J. Signal Process. Syst. 96(1): 67-79 (2024)
2010 – 2019
- 2017
- [j16]Iljung Yoon, Anand Paul
Medical Development Platform Using ZyCAP-Based Partial Reconfiguration on ZynqSoC. Intell. Autom. Soft Comput. 23(2): 365-371 (2017) - [j15]Jooheung Lee
Energy efficient processing of motion estimation for embedded multimedia systems. Multim. Tools Appl. 76(23): 24749-24765 (2017) - [j14]Hyeonggyu Kim
Write-Amount-Aware Management Policies for STT-RAM Caches. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1588-1592 (2017) - 2016
- [j13]Iljung Yoon, Heewon Joung, Jooheung Lee
Zynq-Based Reconfigurable System for Real-Time Edge Detection of Noisy Video Sequences. J. Sensors 2016: 2654059:1-2654059:9 (2016) - 2015
- [j12]Naveed Imran, Rizwan A. Ashraf
Activity-Based Resource Allocation for Motion Estimation Engines. J. Circuits Syst. Comput. 24(1): 1550004:1-1550004:32 (2015) - 2014
- [j11]Naveed Imran, Ronald F. DeMara
Self-Adapting Resource Escalation for Resilient Signal Processing Architectures. J. Signal Process. Syst. 77(3): 257-280 (2014) - 2013
- [j10]Naveed Imran, Jooheung Lee
Fault Demotion Using Reconfigurable Slack (FaDReS). IEEE Trans. Very Large Scale Integr. Syst. 21(7): 1364-1368 (2013) - 2012
- [j9]Junsang Cho, Jungwook Suh, Gwanggil Jeon
Error surface-aware modeling algorithm for quarter-pixel motion estimation. IEEE Trans. Consumer Electron. 58(3): 912-916 (2012) - [j8]Rakan Khraisha, Jooheung Lee
A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration. J. Signal Process. Syst. 66(3): 225-234 (2012) - 2011
- [j7]Jian Huang, Jooheung Lee
Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation. IEEE Embed. Syst. Lett. 3(1): 1-4 (2011) - 2010
- [c10]Ronald F. DeMara, Jooheung Lee, Rawad N. Al-Haddad, Rashad S. Oreifej, Rizwan A. Ashraf, Brian Stensrud, Michael Quist:
Dynamic Partial Reconfiguration Approach to the Design of Sustainable Edge Detectors. ERSA 2010: 49-58 - [c9]Rakan Khraisha, Jooheung Lee
A scalable H.264/AVC deblocking filter architecture using dynamic partial reconfiguration. ICASSP 2010: 1566-1569 - [e1]Toomas P. Plaks, David Andrews, Ronald F. DeMara, Herman Lam, Jooheung Lee, Christian Plessl, Greg Stitt:
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2010, July 12-15, 2010, Las Vegas Nevada, USA. CSREA Press 2010, ISBN 1-60132-140-6 [contents]
2000 – 2009
- 2009
- [j6]Jian Huang, Jooheung Lee
Efficient VLSI architecture for video transcoding. IEEE Trans. Consumer Electron. 55(3): 1462-1470 (2009) - [j5]Jian Huang, Jooheung Lee
A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. IEEE Trans. Circuits Syst. Video Technol. 19(11): 1623-1632 (2009) - [j4]Jian Huang, Matthew Parris, Jooheung Lee
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embed. Comput. Syst. 9(1): 9:1-9:18 (2009) - [c8]Sumedha Gupta Kodipyaka, Jooheung Lee:
A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration. ERSA 2009: 219-225 - [c7]Jian Huang, Jooheung Lee
A Self-Reconfigurable Platform for Scalable DCT Computation Using Compressed Partial Bitstreams and BlockRAM Prefetching. ISVLSI 2009: 67-72 - 2008
- [c6]Jian Huang, Jooheung Lee, Hao Li:
A Fast FPGA Implementation of Tate Pairing in Cryptography over Binary Field. Security and Management 2008: 3-9 - [c5]Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara:
Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. ERSA 2008: 269-272 - [c4]Yidong Liu, Srinivasan Santhanam, Jooheung Lee:
Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study. ERSA 2008: 313-314 - 2006
- [j3]Jooheung Lee
An efficient architecture for motion estimation and compensation in the transform domain. IEEE Trans. Circuits Syst. Video Technol. 16(2): 191-201 (2006) - [j2]Jooheung Lee
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. IEEE Trans. Circuits Syst. Video Technol. 16(5): 655-662 (2006) - [j1]Jooheung Lee
Block-based frequency scalable technique for efficient hierarchical coding. IEEE Trans. Signal Process. 54(7): 2559-2566 (2006) - 2005
- [c3]Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin:
High Performance Array Processor for Video Decoding. ISVLSI 2005: 28-33 - 2004
- [c2]Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin:
Efficient VLSI implementation of inverse discrete cosine transform [image coding applications]. ICASSP (5) 2004: 177-180 - [c1]Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne H. Wolf:
An Architecture for Motion Estimation in the Transform Domain. VLSI Design 2004: 1077-1082
Coauthor Index
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