default search action

combined dblp search
author search
venue search
publication search

ask others

"Scalable FPGA Architecture for DCT Computation Using Dynamic Partial ..."

Jian Huang et al. (2008)

> Home

Details and statistics

DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2009-02-12

- no documents available
- export record
  dblp key:
  - conf/ersa/HuangPLD08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ersa/HuangPLD08
Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara:
Scalable FPGA Architecture for DCT Computation Using Dynamic Partial Reconfiguration. ERSA 2008: 269-272

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.