default search action

combined dblp search
author search
venue search
publication search

ask others

"Scalable FPGA-based architecture for DCT computation using dynamic partial ..."

Jian Huang et al. (2009)

> Home

Details and statistics

DOI: 10.1145/1596532.1596541

access: closed

type: Journal Article

metadata version: 2020-09-08

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tecs/HuangPLD09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tecs/HuangPLD09
Jian Huang, Matthew Parris, Jooheung Lee, Ronald F. DeMara:
Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration. ACM Trans. Embed. Comput. Syst. 9(1): 9:1-9:18 (2009)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.