research-article

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration

Authors:

Matthew Parris,

Ronald F. DemaraAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 9, Issue 1

Article No.: 9, Pages 1 - 18

https://doi.org/10.1145/1596532.1596541

Published: 29 October 2009 Publication History

Abstract

In this article, we propose field programmable gate array-based scalable architecture for discrete cosine transform (DCT) computation using dynamic partial reconfiguration. Our architecture can achieve quality scalability using dynamic partial reconfiguration. This is important for some critical applications that need continuous hardware servicing. Our scalable architecture has three features. First, the architecture can perform DCT computations for eight different zones, that is, from 1 × 1 DCT to 8× 8 DCT. Second, the architecture can change the configuration of processing elements to trade off the precisions of DCT coefficients with computational complexity. Third, unused PEs for DCT can be used for motion estimation computations. Using dynamic partial reconfiguration with 2.3MB bitstreams, 80 distinct hardware architectures can be implemented. We show the experimental results and comparisons between different configurations using both partial reconfiguration and nonpartial reconfiguration process. The detailed trade-offs among visual quality, power consumption, processing clock cycles, and reconfiguration overhead are analyzed in the article.

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Cited By

Kawakami JZajac DLeeser M(2023)Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware2023 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC58863.2023.10363592(1-6)Online publication date: 25-Sep-2023
https://doi.org/10.1109/HPEC58863.2023.10363592
Shi YWang MChen SWei JWang Z(2021)Transform-Based Feature Map Compression for CNN Inference2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401133(1-5)Online publication date: May-2021
https://doi.org/10.1109/ISCAS51556.2021.9401133
Bahar AWahid K(2020)Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular AutomataIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301372428:12(2530-2539)Online publication date: 1-Dec-2020
https://dl.acm.org/doi/10.1109/TVLSI.2020.3013724
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Index Terms

Scalable FPGA-based architecture for DCT computation using dynamic partial reconfiguration
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 9, Issue 1

October 2009

184 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/1596532

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 29 October 2009

Accepted: 01 February 2009

Revised: 01 December 2008

Received: 01 June 2008

Published in TECS Volume 9, Issue 1

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Cited By

Kawakami JZajac DLeeser M(2023)Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware2023 IEEE High Performance Extreme Computing Conference (HPEC)10.1109/HPEC58863.2023.10363592(1-6)Online publication date: 25-Sep-2023
https://doi.org/10.1109/HPEC58863.2023.10363592
Shi YWang MChen SWei JWang Z(2021)Transform-Based Feature Map Compression for CNN Inference2021 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS51556.2021.9401133(1-5)Online publication date: May-2021
https://doi.org/10.1109/ISCAS51556.2021.9401133
Bahar AWahid K(2020)Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular AutomataIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.301372428:12(2530-2539)Online publication date: 1-Dec-2020
https://dl.acm.org/doi/10.1109/TVLSI.2020.3013724
Garnica OLanchares JHidalgo J(2020)Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable DesignsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.296178228:4(914-925)Online publication date: Apr-2020
https://doi.org/10.1109/TVLSI.2019.2961782
Bucknall AShreejith SFahmy S(2020)Build Automation and Runtime Abstraction for Partial Reconfiguration on Xilinx Zynq UltraScale+2020 International Conference on Field-Programmable Technology (ICFPT)10.1109/ICFPT51103.2020.00037(215-220)Online publication date: Dec-2020
https://doi.org/10.1109/ICFPT51103.2020.00037
Lv HZhang SHan WLiu YLiu SZhang LWang S(2020)Design of a Dynamic Reconfigurable Microsystem Based on SIPJournal of Physics: Conference Series10.1088/1742-6596/1549/5/0520321549(052032)Online publication date: 30-Jun-2020
https://doi.org/10.1088/1742-6596/1549/5/052032
Zhang YLi GWang L(2020)A High-Performance with Low-Resource Utility FPGA Implementation of Variable Size HEVC 2D-DCT TransformAdvanced Computer Architecture10.1007/978-981-15-8135-9_24(325-333)Online publication date: 5-Sep-2020
https://doi.org/10.1007/978-981-15-8135-9_24
Ruiz-Rosero JRamirez-Gonzalez GKhanna R(2019)Field Programmable Gate Array Applications—A Scientometric ReviewComputation10.3390/computation70400637:4(63)Online publication date: 11-Nov-2019
https://doi.org/10.3390/computation7040063
Tatulian ASalehi SDeMara R(2019)Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig48160.2019.8994799(1-8)Online publication date: Dec-2019
https://doi.org/10.1109/ReConFig48160.2019.8994799
Shirke SRajabhushnam C(2019)Biometric Personal Iris Recognition from an Image at Long Distance2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI)10.1109/ICOEI.2019.8862640(560-565)Online publication date: Apr-2019
https://doi.org/10.1109/ICOEI.2019.8862640
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