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Chirn Chye Boon
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2020 – today
- 2024
- [j40]Zhe Liu
, Chirn Chye Boon
A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3561-3572 (2024) - 2023
- [j39]Qian Chen
A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS. IEEE J. Solid State Circuits 58(6): 1610-1622 (2023) - [c28]Zhe Liu, Chirn Chye Boon, Yangtao Dong, Kaituo Yang:
A 2.4dB NF +4.1dBm IIP3 Differential Dual-Feedforward-Based Noise-Cancelling LNTA With Complementary NMOS and PMOS Configuration. ESSCIRC 2023: 377-380 - [c27]Oian Chen, Yuan Liang
A Single-Channel 10GS/s 8b>36.4d8 SNDR Time-Domain ADC Featuring Loop-Unrolled Asynchronous Successive Approximation in 28nm CMOS. ISSCC 2023: 278-279 - 2022
- [j38]Qian Chen
A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS. IEEE Access 10: 88558-88566 (2022) - [j37]Gibran Limi Jaya
An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3901-3914 (2022) - [j36]Zhe Liu
A 0.092-mm2 2-12-GHz Noise-Cancelling Low-Noise Amplifier With Gain Improvement and Noise Reduction. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4013-4017 (2022) - [c26]Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Zhe Liu:
A 2-GHz Dual-Path Sub-Sampling PLL with Ring VCO Phase Noise Suppression. CICC 2022: 1-2 - [c25]Zhe Liu, Chirn Chye Boon, Chenyang Li, Kaituo Yang, Yangtao Dong, Ting Guo:
A 0.0078mm2 3.4mW Wideband Positive-feedback-Based Noise-Cancelling LNA in 28nm CMOS Exploiting Gm Boosting. ISSCC 2022: 1-3 - [c24]Kaituo Yang, Chirn Chye Boon, Zhe Liu, Jiaming Piao, Ting Guo, Yangtao Dong, Chenyang Li, Ao Zhou, Zhijie Yang, Xiaoying Wang, Yufeng Liu:
A Hybrid Coupler-First 5GHz Noise-Cancelling Dual-Mode Receiver with +10dBm in-Band IIP3 in Current-Mode and 1.7dB NF in Voltage-Mode. ISSCC 2022: 438-440 - 2021
- [j35]Lingshan Kong
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. IEEE Access 9: 35814-35823 (2021) - [j34]Ao Zhou
A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique. IEEE Access 9: 137241-137248 (2021) - [j33]Xiaoying Wang
A 20-80 MHz Continuously Tunable Gm-C Low-Pass Filter for Ultra-Low Power WBAN Receiver Front-End. IEEE Access 9: 154136-154142 (2021) - [j32]Kaituo Yang
A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation. IEEE J. Solid State Circuits 56(2): 392-403 (2021) - [j31]Bei Liu
A 2.4-6 GHz Broadband GaN Power Amplifier for 802.11ax Application. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2404-2417 (2021) - [j30]Yangtao Dong
A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation. IEEE Trans. Very Large Scale Integr. Syst. 29(7): 1480-1484 (2021) - [c23]Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Ao Zhou, Xin Ding:
A Cross-Coupled Pair Regeneration Based dB-Linear Programable Gain Amplifier with THD Enhancement. ISCAS 2021: 1-5 - [c22]Yuan Liang
Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer. ISCAS 2021: 1-5 - [c21]Kaituo Yang, Chirn Chye Boon, Guangyin Feng, Chenyang Li, Zhe Liu, Ting Guo, Xiang Yi, Yangtao Dong, Ao Zhou, Xiaoying Wang:
A 1.75dB-NF 25mW 5GHz Transformer-Based Noise- Cancelling CMOS Receiver Front-End. ISSCC 2021: 102-104 - 2020
- [j29]Chenyang Li
Compact Switched-Capacitor Power Detector With Frequency Compensation in 65-nm CMOS. IEEE Access 8: 34197-34203 (2020) - [j28]Xiang Yi
An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 686-698 (2020) - [j27]Lingshan Kong
Design of a Wideband Variable-Gain Amplifier With Self-Compensated Transistor for Accurate dB-Linear Characteristic in 65 nm CMOS Technology. IEEE Trans. Circuits Syst. 67-I(12): 4187-4198 (2020) - [c20]Pilsoon Choi, Bugra Kanargi, Kenneth E. Lee, Chirn Chye Boon, Evelyn Wang, Chuan Seng Tan, Dimitri A. Antoniadis, Eugene A. Fitzgerald:
Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications. BCICTS 2020: 1-4 - [c19]Qian Chen, Yuan Liang, Bongjin Kim, Chirn Chye Boon:
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. ISCAS 2020: 1-5 - [c18]Qian Chen, Chirn Chye Boon, Xueyong Zhang
Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line. ISCAS 2020: 1-5 - [c17]Qian Chen, Yuan Liang, Chirn Chye Boon:
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS. ISCAS 2020: 1-5 - [c16]Yong Chen
A 0.024-mm2 45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. MWSCAS 2020: 687-690
2010 – 2019
- 2019
- [j26]Xiang Yi
A 24/77 GHz Dual-Band Receiver for Automotive Radar Applications. IEEE Access 7: 48053-48059 (2019) - [j25]Haohong Yu
A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 71-75 (2019) - [j24]Devrishi Khanna
A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3423-3436 (2019) - [j23]Yong Chen
A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3991-4004 (2019) - [j22]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j21]Yuan Liang
Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1513-1526 (2019) - [c15]Lingshan Kong, Yong Chen
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS 2019: 153-156 - [c14]Arya Balachandran, Yong Chen
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. APCCAS 2019: 221-224 - 2018
- [j20]Guangyin Feng
A W-Band Switch-Less Dicke Receiver for Millimeter-Wave Imaging in 65 nm CMOS. IEEE Access 6: 39233-39240 (2018) - [j19]Yong Chen
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 3014-3026 (2018) - [j18]Lingshan Kong, Yong Chen
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3196-3206 (2018) - [j17]Arya Balachandran
A 0.013-mm2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 599-603 (2018) - [c13]Yuan Liang, Hao Yu, Chirn Chye Boon, Chenyang Li, Dietmar Kissinger, Yong Wang:
D-Band Surface-Wave Modulator and Signal Source with 40 dB Extinction Ratio and 3.7mW Output Power in 65 nm CMOS. ESSCIRC 2018: 142-145 - 2017
- [j16]Guangyin Feng
Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers. IEEE J. Solid State Circuits 52(3): 769-780 (2017) - [j15]Krishnendu Chakrabarty
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - 2016
- [c12]Sunny Sharma
An on-chip integrated III-V / CMOS 125MSps 6-bit SAR ADC. ISIC 2016: 1-4 - 2015
- [j14]Hang Liu
Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits 50(2): 586-596 (2015) - 2014
- [j13]Y. X. Zhang, Chirn Chye Boon
Design and Analysis of a 2.4 GHz Hybrid Type Automatic amplitude Control VCO with Forward noise Reduction. J. Circuits Syst. Comput. 23(4) (2014) - [j12]Xiang Yi, Chirn Chye Boon
A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology. IEEE J. Solid State Circuits 49(2): 347-359 (2014) - [c11]Pilsoon Choi, Jason H. Gao, Nadesh Ramanathan, Mengda Mao, Shipeng Xu, Chirn Chye Boon
A case for leveraging 802.11p for direct phone-to-phone communications. ISLPED 2014: 207-212 - 2013
- [j11]Dandan Chen, Kiat Seng Yeo
Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1516-1525 (2013) - [c10]Xi Zhu, Chirn Chye Boon, Ayobami Iji, Yichuang Sun, Michael Heimlich
A low-noise amplifier with continuously-tuned input matching frequency and output resonance frequency. ISCAS 2013: 1849-1852 - [c9]Xiang Yi, Chirn Chye Boon
A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS. ISSCC 2013: 354-355 - [c8]Nan Huang, Xiang Yi, Chirn Chye Boon, Xiaojin Zhao, Junyi Sun, Guangyin Feng
Design of a fully integrated CMOS dual K- and W-band lumped wilkinson power divider. MWSCAS 2013: 788-791 - 2012
- [j10]Ming-Der Shieh, Yin-Tsung Hwang, Hanho Lee, Chirn Chye Boon
Implementations of Signal-Processing Algorithms for OFDM Systems. J. Electr. Comput. Eng. 2012: 687172:1-687172:2 (2012) - [j9]Juan Xie, Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon
A low power low phase noise dual-band multiphase VCO. Microelectron. J. 43(12): 1016-1022 (2012) - [j8]Yung Sern Tan, Kiat Seng Yeo
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(6): 1156-1167 (2012) - [j7]Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon
A Low-Power Single-Phase Clock Multiband Flexible Divider. IEEE Trans. Very Large Scale Integr. Syst. 20(2): 376-380 (2012) - [c7]Fanyi Meng
Design of quarter-wavelength resonator filters with coupling controllable paths. APCCAS 2012: 248-251 - [c6]Xiang Yi, Chirn Chye Boon
A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology. ESSCIRC 2012: 293-296 - 2011
- [c5]Ali Meaamar, Chirn Chye Boon
A 3.1-8 GHz CMOS UWB front-end receiver. ISCAS 2011: 1556-1559 - 2010
- [j6]Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 72-82 (2010) - [j5]Ali Meaamar, Chirn Chye Boon
A Wideband Low Power Low-Noise Amplifier in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(4): 773-782 (2010) - [j4]Aaron V. T. Do, Chirn Chye Boon
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2675-2684 (2010) - [j3]Zhenghao Lu, Kiat Seng Yeo
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 461-472 (2010) - [c4]Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo:
A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. VLSI-SoC (Selected Papers) 2010: 1-21 - [c3]Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do:
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. VLSI-SoC (Selected Papers) 2010: 69-99 - [c2]Aaron V. T. Do, Chirn Chye Boon
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. VLSI-SoC 2010: 381-386 - [c1]Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. VLSI-SoC 2010: 387-391
2000 – 2009
- 2005
- [j2]Chirn Chye Boon
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(6): 1042-1048 (2005) - 2004
- [j1]Chirn Chye Boon
RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 85-90 (2004)
Coauthor Index
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last updated on 2024-10-08 21:29 CEST by the dblp team
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