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Quan Pan 0002
Person information
- affiliation: Southern University of Science and Technology, School of Microelectronics, Shenzhen, China
- affiliation (PhD 2014): Hong Kong University of Science and Technology, HKUST, Department of electronics and computer engineering, Hong Kong
Other persons with the same name
- Quan Pan 0001
(aka: Pan Quan 0001) — Northwestern Polytechnical University, School of Automation, Xi'an, China
- Quan Pan 0003 — UNESCO-IHE Institute for Water Education, Delft,Netherlands
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2020 – today
- 2024
- [j19]Liping Zhong
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. IEEE J. Solid State Circuits 59(9): 3008-3020 (2024) - [j18]Shuaizhe Ma, Nianquan Ran, Xi Liu, Yifei Xia, Songqin Xu, Wei Huang, Chen Tan, Jing Li, Zhenyu Yin, Shaoheng Lin, Jianhua Pan, Zhe Chen, Chaoxuan Zhang, Wu Wen, Quan Pan, Zhongming Xue, Xiaoyan Gui, Li Geng, Dan Li:
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 5221-5234 (2024) - [c36]Fuzhan Chen
A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS. CICC 2024: 1-2 - [c35]Hongzhi Wu, Weitao Wu, Liping Zhong, Xuxu Cheng, Yangyi Zhang, Xiongshi Luo, Dongfan Xu, Xindan Yu, Quan Pan:
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. CICC 2024: 1-2 - [c34]Jian Yang, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Pui-In Mak, Rui Paulo Martins, Quan Pan:
A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. CICC 2024: 1-2 - [c33]Xiongshi Luo, Xuewei You, Zhenghao Li, Hamed Mosalam, Dongfan Xu, Taiyang Fan, Hongchang Qiao, Wentao Zhou, Hongzhi Wu, Liping Zhong
7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE. ISSCC 2024: 132-134 - [c32]Liping Zhong
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. ISSCC 2024: 134-136 - [c31]Weitao Wu, Hongzhi Wu, Liping Zhong
13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS. ISSCC 2024: 240-242 - [c30]Xuxu Cheng, Hongzhi Wu, Liping Zhong, Weitao Wu, Quan Pan:
A 2×56Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2 - [c29]Chongyun Zhang, Li Wang, Zilu Liu, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue:
A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2 - [c28]Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan:
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j17]Xiaoyan Gui
A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. IET Circuits Devices Syst. 17(1): 13-28 (2023) - [j16]Dongfan Xu
A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3757-3761 (2023) - [c27]Hongzhi Wu, Weitao Wu, Liping Zhong
A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS. A-SSCC 2023: 1-3 - [c26]Fuzhan Chen
A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS. ESSCIRC 2023: 373-376 - [c25]Shuo Feng, Fuzhan Chen, Quan Pan:
A Power-Efficient $\boldsymbol{4}-\mathbf{V}_{\mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS. ICTA 2023: 190-191 - [c24]Dongshen Zhan, Liping Zhong
A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. ICTA 2023: 192-193 - [c23]Dongfan Xu, Yangyi Zhang, Zhenghao Li, Xiongshi Luo, Pingyi Cai, Hongzhi Wu, Liping Zhong
A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. ISCAS 2023: 1-4 - 2022
- [j15]Qiyao Jiang
Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS. IEEE J. Solid State Circuits 57(9): 2812-2828 (2022) - [j14]Wenbo Xiao
A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 634-644 (2022) - [j13]Hamed Mosalam
A 54-68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 40-44 (2022) - [c22]Shuo Feng, Fuzhan Chen, Zhenghao Li, Wentao Zhou, Dongfan Xu, Chun-Zhang Chen, Xuhui Liu, Hanming Wu, Quan Pan:
A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS. APCCAS 2022: 1-5 - [c21]Leiming Wang, Xiongshi Luo, Dongfan Xu, Zhang Qiu, Yiyang Yan, Quan Pan:
A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS. APCCAS 2022: 333-336 - [c20]Xiongshi Luo, Xuewei You, Jiahan Fu, Zhenghao Li, Liping Zhong
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. ESSCIRC 2022: 497-500 - [c19]Liping Zhong
A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS. ESSCIRC 2022: 501-504 - [c18]Zhengzhe Jia
A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS. ICTA 2022: 104-105 - 2021
- [j12]Hamed Mosalam
A 57-100 GHz 0.13 μm SiGe power amplifier with high output power and efficiency. Microelectron. J. 114: 105128 (2021) - [j11]Junhua Zhu
A 19-48.3-GHz 6th-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3053-3057 (2021) - [j10]Zhenghao Li
A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3058-3062 (2021) - [j9]Juncheng Wang
A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2110-2118 (2021) - [c17]Qi Zhang, Xiongshi Luo, Zhenghao Li, Dongfan Xu, Siqiang Zhu, Leiming Wang, Zhenjiang Mao, Xiaoyan Gui, Dan Li, Hongyu Yu, Quan Pan:
A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. APCCAS 2021: 249-252 - [c16]Fuzhan Chen
Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine. ASICON 2021: 1-4 - [c15]Chuanhao Yu, Zhenyu Yin, Chenfan Cao, Shiti Huang, Quan Pan, Xiaoyan Gui, Li Geng, Dan Li:
A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS. ICTA 2021: 224-225 - [c14]Hongchang Qiao, Chenchang Zhan, Quan Pan, Yutian Chen, Ning Zhang:
An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response. ISCAS 2021: 1-4 - [c13]Danfeng Xu, Yu Kou, Paul Lai, Zichuan Cheng, Tze Yin Cheung, Larry Moser, Yang Zhang, Xiaolong Liu, Man Pio Lam, Haikun Jia, Quan Pan, Wing Hong Szeto, Chi Fai Tang, Ka Fai Mak, Khawar Sarfraz, Tairan Zhu, Ming Kwan, Emily Yim Lee Au, Cormac Conroy, Kai-Keung Chan:
8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. ISSCC 2021: 134-136 - 2020
- [j8]Quan Pan
A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 72-76 (2020) - [j7]Qiwei Huang
A -40 °C to 120 °C, 169 ppm/°C Nano-Ampere CMOS Current Reference. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1494-1498 (2020) - [j6]Junfeng Hu
A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. IEEE Trans. Circuits Syst. II Express Briefs 67-II(9): 1499-1503 (2020) - [j5]Quan Pan
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2099-2108 (2020) - [c12]Jiahan Fu, Pingyi Cai, Xiongshi Luo, Xuewei You, Liping Zhong
A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS. ICTA 2020: 88-89 - [c11]Dongfan Xu, Zhang Qiu, Xiongshi Luo, Xuewei You, Wenbo Xiao, Siqiang Zhu, Minzhe Tang, Zhenghao Li, Quan Pan:
Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier. ICTA 2020: 90-91 - [c10]Dan Li, Shengwei Gao, Yongjun Shi, Xiaoyan Gui, Nan Qi, Zhiyong Li, Quan Pan, Patrick Chiang, Li Geng:
A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. ISCAS 2020: 1-4 - [c9]Xin Wang, Yi Peng, Yuanxi Zhang, Tao Xia, Yifan Wu, Juncheng Wang, Lei Wang, Liujia Song, Lei Zhao, Shenglong Zhuo, Quan Pan, Xuefeng Chen, Patrick Yin Chiang, Rui Bai:
PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. OFC 2020: 1-3
2010 – 2019
- 2019
- [j4]Juncheng Wang
A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1698-1702 (2019) - [c8]Lingshan Kong, Yong Chen
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS 2019: 153-156 - [c7]Shang Hu, Tingyu Yao, Bozhi Yin, Chunyu Song, Lei Zhao, Juncheng Wang, Lei Wang, Rui Bai, Xin Wang, Tao Xia, Yi Peng, Binbin Yao, Yuan Li, Xuefeng Chen, Quan Pan, Nan Qi, Patrick Yin Chiang:
A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. OFC 2019: 1-3 - 2017
- [j3]Yipeng Wang
A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(3): 653-663 (2017) - [c6]Guang Zhu, Quan Pan, John Zhuang, Charlie Zhi, C. Patrick Yue:
A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification. A-SSCC 2017: 81-84 - 2015
- [j2]Yan Lu
A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(3): 707-716 (2015) - [c5]Yipeng Wang, Duona Luo
A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks. ESSCIRC 2015: 152-155 - 2014
- [j1]Li Sun, Quan Pan, Keh-Chung Wang, C. Patrick Yue
A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2139-2149 (2014) - [c4]Quan Pan, Yipeng Wang, Zhengxiong Hou, Li Sun, Liang Wu, Wing-Hung Ki
A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. ESSCIRC 2014: 127-130 - [c3]Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. VLSIC 2014: 1-2 - 2013
- [c2]Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue
A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. ASICON 2013: 1-4 - [c1]Quan Pan, Zhengxiong Hou, Yipeng Wang, C. Patrick Yue
A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical. ASICON 2013: 1-4
Coauthor Index
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