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Raphael Rubin
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2010 – 2019
- 2019
- [c13]Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon:
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT 2019: 153-161 - 2018
- [j4]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). ACM Trans. Reconfigurable Technol. Syst. 11(1): 3:1-3:23 (2018) - 2017
- [j3]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Self-Adaptive Timing Repair. IEEE Des. Test 34(6): 54-62 (2017) - [c12]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA 2017: 85-94 - 2016
- [c11]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). FCCM 2016: 111-118 - [c10]Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, André DeHon:
Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. FPGA 2016: 100-104 - 2015
- [c9]Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
Architectural Support for Software-Defined Metadata Processing. ASPLOS 2015: 487-502 - 2014
- [c8]Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
PUMP: a programmable unit for metadata processing. HASP@ISCA 2014: 8:1-8:8 - 2012
- [c7]Nikil Mehta, Raphael Rubin, André DeHon:
Limit study of energy & delay benefits of component-specific routing. FPGA 2012: 97-106 - 2011
- [j2]Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: Lightweight load-time defect avoidance. ACM Trans. Reconfigurable Technol. Syst. 4(4): 33:1-33:24 (2011) - [c6]Raphael Rubin, André DeHon:
Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. FPGA 2011: 173-176 - [p1]Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon:
Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging. Low-Power Variation-Tolerant Design in Nanometer Silicon 2011: 381-432
2000 – 2009
- 2009
- [c5]Raphael Rubin, André DeHon:
Choose-your-own-adventure routing: lightweight load-time defect avoidance. FPGA 2009: 23-32 - 2006
- [c4]Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Tomás E. Uribe, Thomas F. Knight Jr., André DeHon:
GraphStep: A System Architecture for Sparse-Graph Algorithms. FCCM 2006: 143-151 - [c3]Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, André DeHon:
Packet Switched vs. Time Multiplexed FPGA Overlay Networks. FCCM 2006: 205-216 - [c2]Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto:
3D Nanowire-Based Programmable Logic. Nano-Net 2006: 1-5 - 2004
- [j1]André DeHon, Raphael Rubin:
Design of FPGA interconnect for multilevel metallization. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1038-1050 (2004) - 2003
- [c1]Raphael Rubin, André DeHon:
Design of FPGA interconnect for multilevel metalization. FPGA 2003: 154-163
Coauthor Index
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