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Hans Giesen
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2020 – today
- 2021
- [c7]Nik Sultana, John Sonchack, Hans Giesen, Isaac Pedisich, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, André DeHon, Boon Thau Loo
:
Flightplan: Dataplane Disaggregation and Placement for P4 Programs. NSDI 2021: 571-592 - [i1]André DeHon, Hans Giesen, Nik Sultana, Yuanlong Xiao:
Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. CoRR abs/2104.01929 (2021)
2010 – 2019
- 2019
- [c6]Yuanlong Xiao
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. FPT 2019: 153-161 - 2018
- [j2]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). ACM Trans. Reconfigurable Technol. Syst. 11(1): 3:1-3:23 (2018) - [c5]Hans Giesen, Lei Shi, John Sonchack, Anirudh Chelluri, Nishanth Prabhu, Nik Sultana, Latha A. Kant, Anthony J. McAuley, Alexander Poylisher, André DeHon, Boon Thau Loo
In-network computing to the rescue of faulty links. NetCompute@SIGCOMM 2018: 1-6 - 2017
- [j1]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon
Self-Adaptive Timing Repair. IEEE Des. Test 34(6): 54-62 (2017) - [c4]Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. FPGA 2017: 85-94 - 2016
- [c3]Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). FCCM 2016: 111-118 - 2015
- [c2]Yao-Hong Liu
13.2 A 3.7mW-RX 4.4mW-TX fully integrated Bluetooth Low-Energy/IEEE802.15.4/proprietary SoC with an ADPLL-based fast frequency offset compensation in 40nm CMOS. ISSCC 2015: 1-3 - [c1]Christian Bachmann
A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS. VLSIC 2015: 94-
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