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Udit Dhawan
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2010 – 2019
- 2018
- [i1]Ishwar Bhati, Udit Dhawan, Jayesh Gaur, Sreenivas Subramoney, Hong Wang:
MARS: Memory Aware Reordered Source. CoRR abs/1808.03518 (2018) - 2015
- [j2]Udit Dhawan, André DeHon:
Area-Efficient Near-Associative Memories on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(4): 30:1-30:22 (2015) - [c6]Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
Architectural Support for Software-Defined Metadata Processing. ASPLOS 2015: 487-502 - 2014
- [j1]Sharad Sinha, Udit Dhawan, Thambipillai Srikanthan:
Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. J. Circuits Syst. Comput. 23(9) (2014) - [c5]Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, André DeHon:
PUMP: a programmable unit for metadata processing. HASP@ISCA 2014: 8:1-8:8 - 2013
- [c4]Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., André DeHon:
Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security. CCS 2013: 721-732 - [c3]Udit Dhawan, André DeHon:
Area-efficient near-associative memories on FPGAs. FPGA 2013: 191-200 - 2012
- [c2]Udit Dhawan, Albert Kwon, Edin Kadric, Catalin Hritcu, Benjamin C. Pierce, Jonathan M. Smith, André DeHon, Gregory Malecha
, Greg Morrisett, Thomas F. Knight Jr., Andrew Sutherland, Tom Hawkins, Amanda Zyxnfryx, David K. Wittenberg, Peter Trei, Sumit Ray, Greg Sullivan:
Hardware Support for Safety Interlocks and Introspection. SASO Workshops 2012: 1-8 - 2011
- [c1]Sharad Sinha
A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. ISVLSI 2011: 278-283
Coauthor Index
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